add ports function to DummyPLL

diff --git a/src/soc/clock/select.py b/src/soc/clock/select.py
index 463852cf93500f23713d3377e2d021bd51c18818..23286b7a79906b4f0281eb2a8ebd6fb6931188dc 100644 (file)
--- a/src/soc/clock/select.py
+++ b/src/soc/clock/select.py
@@ -88,6 +88,9 @@ class DummyPLL(Elaboratable):
 
         return m
 
+    def ports(self):
+        return [self.clk_24_i, self.clk_pll_o]
+
 
 if __name__ == '__main__':
     dut = ClockSelect()