Add and or and xor to main_stage

diff --git a/src/soc/alu/formal/proof_main_stage.py b/src/soc/alu/formal/proof_main_stage.py
index 372cf99338102a926cf86191a77dd935dcb19890..11d2c61dc77d49269a78a57f4c49edc4190ef516 100644 (file)
--- a/src/soc/alu/formal/proof_main_stage.py
+++ b/src/soc/alu/formal/proof_main_stage.py
@@ -59,9 +59,16 @@ class Driver(Elaboratable):
             dut_sig = getattr(dut.o.ctx.op, name)
             comb += Assert(dut_sig == rec_sig)
 
-        with m.If(rec.insn_type == InternalOp.OP_ADD):
-            comb += Assert(Cat(dut.o.o, dut.o.carry_out) ==
-                           (a + b + carry_in))
+        with m.Switch(rec.insn_type):
+            with m.Case(InternalOp.OP_ADD):
+                comb += Assert(Cat(dut.o.o, dut.o.carry_out) ==
+                               (a + b + carry_in))
+            with m.Case(InternalOp.OP_AND):
+                comb += Assert(dut.o.o == a & b)
+            with m.Case(InternalOp.OP_OR):
+                comb += Assert(dut.o.o == a | b)
+            with m.Case(InternalOp.OP_XOR):
+                comb += Assert(dut.o.o == a ^ b)
 
 
         return m

diff --git a/src/soc/alu/main_stage.py b/src/soc/alu/main_stage.py
index d443e9777476a8b608cae760289fe0c4255fa777..615a78452279b7ca32b9cfe07a8d4b7493932d8c 100644 (file)
--- a/src/soc/alu/main_stage.py
+++ b/src/soc/alu/main_stage.py
@@ -27,6 +27,12 @@ class ALUMainStage(PipeModBase):
             with m.Case(InternalOp.OP_ADD):
                 comb += self.o.o.eq(add_output[0:64])
                 comb += self.o.carry_out.eq(add_output[64])
+            with m.Case(InternalOp.OP_AND):
+                comb += self.o.o.eq(self.i.a & self.i.b)
+            with m.Case(InternalOp.OP_OR):
+                comb += self.o.o.eq(self.i.a | self.i.b)
+            with m.Case(InternalOp.OP_XOR):
+                comb += self.o.o.eq(self.i.a ^ self.i.b)
 
 
         comb += self.o.ctx.eq(self.i.ctx)