fixup XER names in shift_rot pipe tests

diff --git a/src/soc/fu/shift_rot/input_stage.py b/src/soc/fu/shift_rot/input_stage.py
index dde412969f9e42b47b1cdaef09f5cc9c630dd239..83df5a7fe162b70674ba18e3541bb87577692a71 100644 (file)
--- a/src/soc/fu/shift_rot/input_stage.py
+++ b/src/soc/fu/shift_rot/input_stage.py
@@ -44,15 +44,15 @@ class ShiftRotInputStage(PipeModBase):
         # either copy incoming carry or set to 1/0 as defined by op
         with m.Switch(self.i.ctx.op.input_carry):
             with m.Case(CryIn.ZERO):
-                comb += self.o.carry_in.eq(0)
+                comb += self.o.xer_ca.eq(0b00)
             with m.Case(CryIn.ONE):
-                comb += self.o.carry_in.eq(1)
+                comb += self.o.xer_ca.eq(0b11) # XER CA/CA32
             with m.Case(CryIn.CA):
-                comb += self.o.carry_in.eq(self.i.carry_in)
+                comb += self.o.xer_ca.eq(self.i.xer_ca)
 
         ##### sticky overflow and context (both pass-through) #####
 
-        comb += self.o.so.eq(self.i.so)
+        comb += self.o.xer_so.eq(self.i.xer_so)
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m

diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py
index f39118271eb188351679781734b33cf896901794..be5b47d54b871c23fde2d6124bd460851f39cf14 100644 (file)
--- a/src/soc/fu/shift_rot/main_stage.py
+++ b/src/soc/fu/shift_rot/main_stage.py
@@ -67,12 +67,13 @@ class ShiftRotMainStage(PipeModBase):
                     rotator.clear_right).eq(mode)
                 
         # outputs from the microwatt rotator module
+        # XXX TODO: carry32
         comb += [self.o.o.eq(rotator.result_o),
-                 self.o.xer_co.eq(rotator.carry_out_o)]
+                 self.o.xer_ca[0].eq(rotator.carry_out_o)]
 
         ###### sticky overflow and context, both pass-through #####
 
-        comb += self.o.xer_so.data.eq(self.i.so)
+        comb += self.o.xer_so.data.eq(self.i.xer_so)
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m

diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index 42b70db6f3c6487821a27eafd152b014c6328cdf..0c0e6cab54db84a05bce85ae1b8bc1276540c3b8 100644 (file)
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -11,20 +11,20 @@ class ShiftRotInputData(IntegerData):
         self.ra = Signal(64, reset_less=True) # RA
         self.rs = Signal(64, reset_less=True) # RS
         self.rb = Signal(64, reset_less=True) # RB/immediate
-        self.so = Signal(reset_less=True)
-        self.carry_in = Signal(reset_less=True)
+        self.xer_so = Signal(reset_less=True)    # XER bit 32: SO
+        self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
 
     def __iter__(self):
         yield from super().__iter__()
         yield self.ra
         yield self.rs
         yield self.rb
-        yield self.carry_in
-        yield self.so
+        yield self.xer_ca
+        yield self.xer_so
 
     def eq(self, i):
         lst = super().eq(i)
         return lst + [self.rs.eq(i.rs), self.ra.eq(i.ra),
                       self.rb.eq(i.rb),
-                      self.carry_in.eq(i.carry_in),
-                      self.so.eq(i.so)]
+                      self.xer_ca.eq(i.xer_ca),
+                      self.xer_so.eq(i.xer_so)]

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index def0256cef2aa18be381dd46945d4084e1f2bf2b..f8c2880bad908e5fe609cd17a45f43f376b33d51 100644 (file)
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -67,9 +67,11 @@ def set_alu_inputs(alu, dec2, sim):
 
 def set_extra_alu_inputs(alu, dec2, sim):
     carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
-    yield alu.p.data_i.carry_in.eq(carry)
+    carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
+    yield alu.p.data_i.xer_ca[0].eq(carry)
+    yield alu.p.data_i.xer_ca[1].eq(carry32)
     so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
-    yield alu.p.data_i.so.eq(so)
+    yield alu.p.data_i.xer_so.eq(so)
     
 
 # This test bench is a bit different than is usual. Initially when I
@@ -79,7 +81,7 @@ def set_extra_alu_inputs(alu, dec2, sim):
 # should have. However, this was really slow, since it needed to
 # create and tear down the dut and simulator for every test case.
 
-# Now, instead of doing that, every test case in ALUTestCase puts some
+# Now, instead of doing that, every test case in ShiftRotTestCase puts some
 # data into the test_data list below, describing the instructions to
 # be tested and the initial state. Once all the tests have been run,
 # test_data gets passed to TestRunner which then sets up the DUT and
@@ -93,7 +95,7 @@ def set_extra_alu_inputs(alu, dec2, sim):
 test_data = []
 
 
-class ALUTestCase(FHDLTestCase):
+class ShiftRotTestCase(FHDLTestCase):
     def __init__(self, name):
         super().__init__(name)
         self.test_name = name