fix bug in mmu/fsm.py

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index 30ec48536b56608015caf6ee0a6bfb120a764ef3..5f426a749241ebaa8e68ad5642d04ffea3386150 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -310,7 +310,7 @@ class FSMMMUStage(ControlBase):
         msr_i = op.msr
         spr1_i = data_i.spr1
 
-        # TODO: link these SPRs somewhere
+        # FIXME: unused signals -> remove if not needed
         dsisr = Signal(64)
         dar = Signal(64)
 
@@ -355,7 +355,7 @@ class FSMMMUStage(ControlBase):
                     # regfile because the CSV file entry for OP_MTSPR
                     # categorically defines and requires the expectation
                     # that the CompUnit **WILL** write to the regfile.
-                    comb += spr1_o.data.eq(spr)
+                    comb += spr1_o.data.eq(a_i)
                     comb += spr1_o.ok.eq(1)
                     # subset SPR: first check a few bits
                     with m.If(~spr[9] & ~spr[5]):