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fix setting of SVSTATE.VL and MVL
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 12 Feb 2021 12:55:01 +0000 (12:55 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 12 Feb 2021 12:55:01 +0000 (12:55 +0000)
src/soc/decoder/isa/caller.py patch | blob | history
src/soc/decoder/isa/test_caller_svp64.py patch | blob | history

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 41f129df80932bbea3c1bc562338922ceadeae56..e9afcf21f1202bf3fecd57a9a175a34e9771be6a 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -697,6 +697,8 @@ class ISACaller:
 
         # in SVP64 mode.  decode/print out svp64 prefix, get v3.0B instruction
         print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
 
         # in SVP64 mode.  decode/print out svp64 prefix, get v3.0B instruction
         print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
+        print ("    svstate.vl", self.svstate.vl.asint(msb0=True))
+        print ("    svstate.mvl", self.svstate.maxvl.asint(msb0=True))
         sv_rm = pfx.rm.asint()
         ins = self.imem.ld(pc+4, 4, False, True)
         print("     svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
         sv_rm = pfx.rm.asint()
         ins = self.imem.ld(pc+4, 4, False, True)
         print("     svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
diff --git a/src/soc/decoder/isa/test_caller_svp64.py b/src/soc/decoder/isa/test_caller_svp64.py
index 34af4831a3d2e2cd10f44ac5c478a0dd6de85881..1804461558ee0e55b4a2dbcececbecea6f38f9d2 100644 (file)
--- a/src/soc/decoder/isa/test_caller_svp64.py
+++ b/src/soc/decoder/isa/test_caller_svp64.py
@@ -26,8 +26,8 @@ class DecoderTestCase(FHDLTestCase):
         initial_regs[3] = 0x1234
         initial_regs[2] = 0x4321
         svstate = SVP64State()
         initial_regs[3] = 0x1234
         initial_regs[2] = 0x4321
         svstate = SVP64State()
-        svstate.vl[0:-1] = 2 # VL
-        svstate.maxvl[0:-1] = 2 # MAXVL
+        svstate.vl[0:7] = 2 # VL
+        svstate.maxvl[0:7] = 2 # MAXVL
         print ("SVSTATE", bin(svstate.spr.asint()))
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_regs, svstate)
         print ("SVSTATE", bin(svstate.spr.asint()))
         with Program(lst, bigendian=False) as program:
             sim = self.run_tst_program(program, initial_regs, svstate)