Add right shift test to test_caller.py

diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index 467d6d210c6a38d5585284303ce56ba384349f2a..7e5534a61cac5677d931f41e0498c9a4381a133c 100644 (file)
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -187,7 +187,7 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_tst_program(program)
             self.assertEqual(sim.gpr(3), SelectableInt(0x20000000, 64))
 
             sim = self.run_tst_program(program)
             self.assertEqual(sim.gpr(3), SelectableInt(0x20000000, 64))
 

-    def test_shift(self):
+    def test_slw(self):

         lst = ["slw 1, 3, 2"]
         initial_regs = [0] * 32
         initial_regs[3] = 0xdeadbeefcafebabe
         lst = ["slw 1, 3, 2"]
         initial_regs = [0] * 32
         initial_regs[3] = 0xdeadbeefcafebabe


@@ -196,6 +196,15 @@ class DecoderTestCase(FHDLTestCase):
             sim = self.run_tst_program(program, initial_regs)
             self.assertEqual(sim.gpr(1), SelectableInt(0x5fd757c0, 32))
 
             sim = self.run_tst_program(program, initial_regs)
             self.assertEqual(sim.gpr(1), SelectableInt(0x5fd757c0, 32))
 

+    def test_srw(self):
+        lst = ["srw 1, 3, 2"]
+        initial_regs = [0] * 32
+        initial_regs[3] = 0xdeadbeefcafebabe
+        initial_regs[2] = 5
+        with Program(lst) as program:
+            sim = self.run_tst_program(program, initial_regs)
+            self.assertEqual(sim.gpr(1), SelectableInt(0x657f5d5, 32))
+

     def test_mtcrf(self):
         for i in range(4):
             # 0x76540000 gives expected (3+4) (2+4) (1+4) (0+4) for
     def test_mtcrf(self):
         for i in range(4):
             # 0x76540000 gives expected (3+4) (2+4) (1+4) (0+4) for