rename and add pll lock signal to ls180

diff --git a/src/soc/clock/dummypll.py b/src/soc/clock/dummypll.py
index db81eefb69ca3f050bd247731f26cb1a864e8a1f..8594f91e78638d0355919dbfa187d515aeea0862 100644 (file)
--- a/src/soc/clock/dummypll.py
+++ b/src/soc/clock/dummypll.py
@@ -10,7 +10,7 @@ class DummyPLL(Elaboratable):
         self.clk_sel_i = Signal(2, reset_less=True) # PLL selection
         self.clk_pll_o = Signal(reset_less=True)  # output fake PLL clock
         self.pll_18_o = Signal(reset_less=True)  # 16-divide from PLL
         self.clk_sel_i = Signal(2, reset_less=True) # PLL selection
         self.clk_pll_o = Signal(reset_less=True)  # output fake PLL clock
         self.pll_18_o = Signal(reset_less=True)  # 16-divide from PLL

-        self.clk_lck_o = Signal(reset_less=True)  # output fake PLL "lock" 
+        self.pll_lck_o = Signal(reset_less=True)  # output fake PLL "lock"

 
     def elaborate(self, platform):
         m = Module()
 
     def elaborate(self, platform):
         m = Module()


@@ -18,7 +18,7 @@ class DummyPLL(Elaboratable):
         # just get something, stops yosys destroying (optimising) these out
         m.d.comb += self.pll_18_o.eq(self.clk_24_i)
         with m.If(self.clk_sel_i == Const(0, 2)):
         # just get something, stops yosys destroying (optimising) these out
         m.d.comb += self.pll_18_o.eq(self.clk_24_i)
         with m.If(self.clk_sel_i == Const(0, 2)):

-            m.d.comb += self.clk_lck_o.eq(self.clk_24_i)
+            m.d.comb += self.pll_lck_o.eq(self.clk_24_i)

 
         return m
 
 
         return m
 

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index b01c5fc8a7811db043d47b6e6a061d88ba107bd6..12112b6610be8a917b3a8425e42b960bfd37244d 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -241,8 +241,10 @@ class LibreSoC(CPU):
         if variant == "ls180":
             self.pll_18_o = Signal()
             self.clk_sel = Signal(3)
         if variant == "ls180":
             self.pll_18_o = Signal()
             self.clk_sel = Signal(3)

+            self.pll_lck_o = Signal()

             self.cpu_params['i_clk_sel_i'] = self.clk_sel
             self.cpu_params['o_pll_18_o'] = self.pll_18_o
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
             self.cpu_params['o_pll_18_o'] = self.pll_18_o

+            self.cpu_params['o_pll_lck_o'] = self.pll_lck_o

 
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus))
 
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus))

diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py
index f8580d37a35ea6783f5d33e7e1e729917eac91e0..3eb9abeb8a270c248d69b5bfadf5b11852f118cd 100644 (file)
--- a/src/soc/litex/florent/libresoc/ls180.py
+++ b/src/soc/litex/florent/libresoc/ls180.py
@@ -51,6 +51,7 @@ def io():
         ("sys_rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
         ("sys_clksel_i",   0, Pins("R1 R2 R3"), IOStandard("LVCMOS33")),
         ("sys_pll_18_o",   0, Pins("R1"), IOStandard("LVCMOS33")),
         ("sys_rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
         ("sys_clksel_i",   0, Pins("R1 R2 R3"), IOStandard("LVCMOS33")),
         ("sys_pll_18_o",   0, Pins("R1"), IOStandard("LVCMOS33")),

+        ("sys_pll_lck_o",   0, Pins("R1"), IOStandard("LVCMOS33")),

 
         # JTAG0: 4 pins
         ("jtag", 0,
 
         # JTAG0: 4 pins
         ("jtag", 0,

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 52c83ea40a60e65d422857ba845f7e54b76268c2..eb2afafb934520213eeb680655a0c843ecfe532a 100755 (executable)
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -366,9 +366,11 @@ class LibreSoCSim(SoCCore):
         # PLL/Clock Select
         clksel_i = platform.request("sys_clksel_i")
         pll18_o = platform.request("sys_pll_18_o")
         # PLL/Clock Select
         clksel_i = platform.request("sys_clksel_i")
         pll18_o = platform.request("sys_pll_18_o")

+        pll_lck_o = platform.request("sys_pll_lck_o")

 
         self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
         self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from the PLL
 
         self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
         self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from the PLL

+        self.comb += pll_lck_o.eq(self.cpu.pll_lck_o) # PLL lock flag

 
         #ram_init = []
 
 
         #ram_init = []
 

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index c231702f49f10fbac273da58e8da5f6e97ce50d2..5a62fdcd8a418cd72328932cd65c028e4ea456c6 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -513,7 +513,7 @@ class TestIssuer(Elaboratable):
         if self.pll_en:
             ports.append(self.pll.clk_sel_i)
             ports.append(self.pll.pll_18_o)
         if self.pll_en:
             ports.append(self.pll.clk_sel_i)
             ports.append(self.pll.pll_18_o)

-            ports.append(self.pll.clk_lck_o)
+            ports.append(self.pll.pll_lck_o)

         return ports
 
 
         return ports