remove sticky overflow from Shift Rot pipeline

diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py
index 10949c550a5580f2e9935a4fd47a3308184d1724..16b455301e68516fad05166b3c994984ca49bc0a 100644 (file)
--- a/src/soc/fu/shift_rot/main_stage.py
+++ b/src/soc/fu/shift_rot/main_stage.py
@@ -4,7 +4,7 @@
 # output stage
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
 from nmutil.pipemodbase import PipeModBase
-from soc.fu.alu.pipe_data import ALUOutputData
+from soc.fu.logical.pipe_data import LogicalOutputData
 from soc.fu.shift_rot.pipe_data import ShiftRotInputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.decoder.power_enums import InternalOp
@@ -24,7 +24,7 @@ class ShiftRotMainStage(PipeModBase):
         return ShiftRotInputData(self.pspec)
 
     def ospec(self):
-        return ALUOutputData(self.pspec) # TODO: ALUIntermediateData
+        return LogicalOutputData(self.pspec)
 
     def elaborate(self, platform):
         m = Module()
@@ -74,7 +74,6 @@ class ShiftRotMainStage(PipeModBase):
 
         ###### sticky overflow and context, both pass-through #####
 
-        comb += self.o.xer_so.data.eq(self.i.xer_so)
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m

diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index 1375ae0a26041c2a8dcfab1743103040ec8b1574..ed3cd14ddf2216047f5093f2c119da8b684ccacf 100644 (file)
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -11,14 +11,12 @@ class ShiftRotInputData(IntegerData):
     regspec = [('INT', 'a', '0:63'),
                ('INT', 'rs', '0:63'),
                ('INT', 'rb', '0:63'),
-               ('XER', 'xer_so', '32'),
                ('XER', 'xer_ca', '34,45')]
     def __init__(self, pspec):
         super().__init__(pspec)
         self.a = Signal(64, reset_less=True) # RA
         self.rs = Signal(64, reset_less=True) # RS
         self.rb = Signal(64, reset_less=True) # RB/immediate
-        self.xer_so = Signal(reset_less=True)    # XER bit 32: SO
         self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
 
     def __iter__(self):
@@ -27,14 +25,12 @@ class ShiftRotInputData(IntegerData):
         yield self.rs
         yield self.rb
         yield self.xer_ca
-        yield self.xer_so
 
     def eq(self, i):
         lst = super().eq(i)
         return lst + [self.rs.eq(i.rs), self.a.eq(i.a),
                       self.rb.eq(i.rb),
-                      self.xer_ca.eq(i.xer_ca),
-                      self.xer_so.eq(i.xer_so)]
+                      self.xer_ca.eq(i.xer_ca) ]
 
 
 # TODO: replace CompALUOpSubset with CompShiftRotOpSubset

diff --git a/src/soc/fu/shift_rot/pipeline.py b/src/soc/fu/shift_rot/pipeline.py
index 316fb832918c4df0ac6828f29e2c339d3044ac7b..0449d37d964191fea1fb866f42292c201718100b 100644 (file)
--- a/src/soc/fu/shift_rot/pipeline.py
+++ b/src/soc/fu/shift_rot/pipeline.py
@@ -2,13 +2,13 @@ from nmutil.singlepipe import ControlBase
 from nmutil.pipemodbase import PipeModBaseChain
 from soc.fu.shift_rot.input_stage import ShiftRotInputStage
 from soc.fu.shift_rot.main_stage import ShiftRotMainStage
-from soc.fu.alu.output_stage import ALUOutputStage
+from soc.fu.logical.output_stage import LogicalOutputStage
 
 class ShiftRotStages(PipeModBaseChain):
     def get_chain(self):
         inp = ShiftRotInputStage(self.pspec)
         main = ShiftRotMainStage(self.pspec)
-        out = ALUOutputStage(self.pspec)
+        out = LogicalOutputStage(self.pspec)
         return [inp, main, out]
 
 

diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py
index fb370525bade385e5e6d7bd9f6049c633d0a6e3e..2d6fb8e126a4b7283bde0a42f11e4bde4e0d4a50 100644 (file)
--- a/src/soc/fu/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py
@@ -63,8 +63,6 @@ def set_extra_alu_inputs(alu, dec2, sim):
     carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
     yield alu.p.data_i.xer_ca[0].eq(carry)
     yield alu.p.data_i.xer_ca[1].eq(carry32)
-    so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
-    yield alu.p.data_i.xer_so.eq(so)
     
 
 # This test bench is a bit different than is usual. Initially when I