Fix indentation of regfile/formal/proof_regfile.py

diff --git a/src/soc/regfile/formal/proof_regfile.py b/src/soc/regfile/formal/proof_regfile.py
index 6ecad092f5f5bfd5911d635854ffb0ee13a337c7..e37ea47db30cf49660e4502215e82abe893240c0 100644 (file)
--- a/src/soc/regfile/formal/proof_regfile.py
+++ b/src/soc/regfile/formal/proof_regfile.py
@@ -8,7 +8,7 @@ from nmigen.test.utils import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest
 
-from soc.regfile import Register
+from soc.regfile.regfile import Register
 
 
 class Driver(Elaboratable):
@@ -44,17 +44,17 @@ class Driver(Elaboratable):
         return m
 
 
-    def TestCase(FHDLTestCase):
-        def test_formal(self):
-            module = Driver()
-            self.assertFormal(module, mode="bmc", depth=2)
-            self.assertFormal(module, mode="cover", depth=2)
+class TestCase(FHDLTestCase):
+    def test_formal(self):
+        module = Driver()
+        self.assertFormal(module, mode="bmc", depth=2)
+        self.assertFormal(module, mode="cover", depth=2)
 
-        def test_ilang(self):
-            dut = Driver()
-            vl = rtlil.convert(dut, ports=[])
-            with open("regfile.il", "w") as f:
-                f.write(vl)
+    def test_ilang(self):
+        dut = Driver()
+        vl = rtlil.convert(dut, ports=[])
+        with open("regfile.il", "w") as f:
+            f.write(vl)
 
 
 if __name__ == '__main__':