add divide-by-zero test to test_div_sim.py

diff --git a/src/soc/simulator/test_div_sim.py b/src/soc/simulator/test_div_sim.py
index 2129de3338f266dfd31d22856b47528161feaab7..acaeed7a5a450889f3797a6a8b9937d3cfb2f5b8 100644 (file)
--- a/src/soc/simulator/test_div_sim.py
+++ b/src/soc/simulator/test_div_sim.py
@@ -32,7 +32,15 @@ class DivTestCases(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1, 2, 3])
 
-    def test_0_moduw(self):
+    def test_1_divw_byzero(self):
+        lst = ["addi 1, 0, 0x5678",
+               "addi 2, 0, 0x0",
+               "divw  3, 1, 2",
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1, 2, 3])
+
+    def test_2_moduw(self):
         lst = ["addi 1, 0, 0x5678",
                "addi 2, 0, 0x1234",
                "moduw  3, 1, 2",