whitespace
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 10 Jun 2020 14:51:48 +0000 (15:51 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 10 Jun 2020 14:51:48 +0000 (15:51 +0100)
src/soc/experiment/l0_cache.py

index 3b8ff913f5312545f2ed41467f5f14de8426ad33..d67624bf3a06d4243bfce014bf431c1195ebab9b 100644 (file)
@@ -163,6 +163,7 @@ class DualPortSplitter(Elaboratable):
         #comb += splitter.sst_valid_i.eq()
         return m
 
+
 class DataMergerRecord(Record):
     """
     {data: 128 bit, byte_enable: 16 bit}
@@ -173,11 +174,11 @@ class DataMergerRecord(Record):
                   ('en', 16))
         Record.__init__(self, Layout(layout), name=name)
 
-        self.data.reset_less=True
-        self.en.reset_less=True
+        self.data.reset_less = True
+        self.en.reset_less = True
 
-# TODO: formal verification
 
+# TODO: formal verification
 class DataMerger(Elaboratable):
     """DataMerger
 
@@ -617,6 +618,7 @@ class TestL0Cache(unittest.TestCase):
         run_simulation(dut, l0_cache_ldst(self, dut),
                        vcd_name='test_l0_cache_basic.vcd')
 
+
 class TestDataMerger(unittest.TestCase):
 
     def test_data_merger(self):
@@ -642,6 +644,7 @@ class TestDualPortSplitter(unittest.TestCase):
         #run_simulation(dut, data_merger_merge(dut),
         #               vcd_name='test_dual_port_splitter.vcd')
 
+
 if __name__ == '__main__':
     unittest.main(exit=False)