Memory port seems to have been renamed

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 41b5a76aaa3115fcd58b6aa73f27fe1f0c5977e7..eb75d3b42977f9a7be17b6a7d02fead13b42c6ce 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -395,17 +395,17 @@ class TestRunner(FHDLTestCase):
             {'comment': 'instruction memory'},
             'imem.sram.rdport.memory(0)[63:0]',
             {'comment': 'registers'},
-            'core.int.rp_src1.memory(0)[63:0]',
-            'core.int.rp_src1.memory(1)[63:0]',
-            'core.int.rp_src1.memory(2)[63:0]',
-            'core.int.rp_src1.memory(3)[63:0]',
-            'core.int.rp_src1.memory(4)[63:0]',
-            'core.int.rp_src1.memory(5)[63:0]',
-            'core.int.rp_src1.memory(6)[63:0]',
-            'core.int.rp_src1.memory(7)[63:0]',
-            'core.int.rp_src1.memory(9)[63:0]',
-            'core.int.rp_src1.memory(10)[63:0]',
-            'core.int.rp_src1.memory(13)[63:0]',
+            'core.int.rp_src.memory(0)[63:0]',
+            'core.int.rp_src.memory(1)[63:0]',
+            'core.int.rp_src.memory(2)[63:0]',
+            'core.int.rp_src.memory(3)[63:0]',
+            'core.int.rp_src.memory(4)[63:0]',
+            'core.int.rp_src.memory(5)[63:0]',
+            'core.int.rp_src.memory(6)[63:0]',
+            'core.int.rp_src.memory(7)[63:0]',
+            'core.int.rp_src.memory(9)[63:0]',
+            'core.int.rp_src.memory(10)[63:0]',
+            'core.int.rp_src.memory(13)[63:0]',
         ]
 
         if self.microwatt_mmu: