rename spr1 to fast1 in trap data

diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py
index 3b336e2ba6049fb2f32ec7b2d6eeae25cc3d39d9..a43c214c65031f0c8ba99526a75bb95dee462a35 100644 (file)
--- a/src/soc/fu/trap/pipe_data.py
+++ b/src/soc/fu/trap/pipe_data.py
@@ -5,27 +5,27 @@ from soc.fu.trap.trap_input_record import CompTrapOpSubset
 class TrapInputData(IntegerData):
     regspec = [('INT', 'ra', '0:63'),  # RA
                ('INT', 'rb', '0:63'),  # RB/immediate
-               ('FAST', 'spr1', '0:63'), # SRR0
-               ('FAST', 'spr2', '0:63'), # SRR1
+               ('FAST', 'fast1', '0:63'), # SRR0
+               ('FAST', 'fast2', '0:63'), # SRR1
                ('FAST', 'cia', '0:63'),  # Program counter (current)
                ('FAST', 'msr', '0:63')]  # MSR
     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience
-        self.srr0, self.srr1 = self.spr1, self.spr2
+        self.srr0, self.srr1 = self.fast1, self.fast2
         self.a, self.b = self.ra, self.rb
 
 
 class TrapOutputData(IntegerData):
     regspec = [('INT', 'o', '0:63'),     # RA
-               ('FAST', 'spr1', '0:63'), # SRR0 SPR
-               ('FAST', 'spr2', '0:63'), # SRR1 SPR
+               ('FAST', 'fast1', '0:63'), # SRR0 SPR
+               ('FAST', 'fast2', '0:63'), # SRR1 SPR
                ('FAST', 'nia', '0:63'),  # NIA (Next PC)
                ('FAST', 'msr', '0:63')]  # MSR
     def __init__(self, pspec):
         super().__init__(pspec, True)
         # convenience
-        self.srr0, self.srr1 = self.spr1, self.spr2
+        self.srr0, self.srr1 = self.fast1, self.fast2