split out HDL test from Simulator test,

save two separate lists of TestStates
compare them *after* the two simulations have been run
should be possible to completely separate out, now

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index e1e572be33ece86c8b9b623dc6e2d613de825487..20318a37d00853948b3f735b51850e2e7ce7b933 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -34,6 +34,7 @@ from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
 from nmutil.util import wrap
 from soc.experiment.test.test_mmu_dcache import wb_get
+from openpower.test.state import TestState
 
 
 def setup_i_memory(imem, startaddr, instructions):
@@ -217,13 +218,18 @@ class TestRunner(FHDLTestCase):
                     insncode = program.assembly.splitlines()
                     instructions = list(zip(gen, insncode))
 
-                    # set up the Simulator (which must track TestIssuer exactly)
-                    sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
-                              test.msr,
-                              initial_insns=gen, respect_pc=True,
-                              disassembly=insncode,
-                              bigendian=bigendian,
-                              initial_svstate=test.svstate)
+                    # Run two tests (TODO, move these to functions)
+                    # * first the Simulator, collate a batch of results
+                    # * then the HDL, likewise
+                    #   (actually, the other way round because running
+                    #    Simulator somehow modifies the test state!)
+                    # * finally, compare all the results
+
+                    ##########
+                    # 1. HDL
+                    ##########
+
+                    hdl_states = []
 
                     # establish the TestIssuer context (mem, regs etc)
 
@@ -248,11 +254,11 @@ class TestRunner(FHDLTestCase):
                     print("instructions", instructions)
 
                     # run the loop of the instructions on the current test
-                    index = sim.pc.CIA.value//4
+                    index = (yield issuer.cur_state.pc) // 4
                     while index < len(instructions):
                         ins, code = instructions[index]
 
-                        print("instruction: 0x{:X}".format(ins & 0xffffffff))
+                        print("hdl instr: 0x{:X}".format(ins & 0xffffffff))
                         print(index, code)
 
                         if counter == 0:
@@ -271,22 +277,19 @@ class TestRunner(FHDLTestCase):
                         while not (yield issuer.insn_done):
                             yield
 
-                        # set up simulated instruction (in simdec2)
-                        try:
-                            yield from sim.setup_one()
-                        except KeyError:  # instruction not in imem: stop
-                            break
                         yield Settle()
 
-                        # call simulated operation
-                        print("sim", code)
-                        yield from sim.execute_one()
-                        yield Settle()
-                        index = sim.pc.CIA.value//4
+                        index = (yield issuer.cur_state.pc) // 4
 
                         terminated = yield issuer.dbg.terminated_o
                         print("terminated", terminated)
 
+                        if index < len(instructions):
+                            # Get HDL mem and state
+                            state = yield from TestState("hdl", core, self,
+                                                         code)
+                            hdl_states.append(state)
+
                         if index >= len(instructions):
                             print ("index over, send dmi stop")
                             # stop at end
@@ -295,17 +298,69 @@ class TestRunner(FHDLTestCase):
                             yield
                             yield
 
-                        # register check
-                        yield from check_regs(self, sim, core, test, code)
-
-                        # Memory check
-                        yield from check_mem(self, sim, core, test, code)
-
                         terminated = yield issuer.dbg.terminated_o
                         print("terminated(2)", terminated)
                         if terminated:
                             break
 
+                    ##########
+                    # 2. Simulator
+                    ##########
+
+                    sim_states = []
+
+                    # set up the Simulator (which must track TestIssuer exactly)
+                    sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
+                              test.msr,
+                              initial_insns=gen, respect_pc=True,
+                              disassembly=insncode,
+                              bigendian=bigendian,
+                              initial_svstate=test.svstate)
+
+                    # run the loop of the instructions on the current test
+                    index = sim.pc.CIA.value//4
+                    while index < len(instructions):
+                        ins, code = instructions[index]
+
+                        print("sim instr: 0x{:X}".format(ins & 0xffffffff))
+                        print(index, code)
+
+                        # set up simulated instruction (in simdec2)
+                        try:
+                            yield from sim.setup_one()
+                        except KeyError:  # instruction not in imem: stop
+                            break
+                        yield Settle()
+
+                        # call simulated operation
+                        print("sim", code)
+                        yield from sim.execute_one()
+                        yield Settle()
+                        index = sim.pc.CIA.value//4
+
+                        # get sim register and memory TestState, add to list
+                        state = yield from TestState("sim", sim, self, code)
+                        sim_states.append(state)
+
+                    ###############
+                    # 3. Compare
+                    ###############
+
+                    for simstate, hdlstate in zip(sim_states, hdl_states):
+                        simstate.compare(hdlstate)     # register check
+                        simstate.compare_mem(hdlstate) # memory check
+
+                    print ("hdl_states")
+                    for state in hdl_states:
+                        print (state)
+
+                    print ("sim_states")
+                    for state in sim_states:
+                        print (state)
+
+                    self.assertTrue(len(hdl_states) == len(sim_states),
+                                    "number of instructions run not the same")
+
                 # stop at end
                 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
                 yield