testing microwatt 3.bin (2.bin ok)

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index afe4140f9de89e86df49c8afa0fcb43dc74c2661..ce746dd49aa5facf24c78f8ca02f58d23b8d17b7 100755 (executable)
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -49,7 +49,7 @@ class LibreSoCSim(SoCSDRAM):
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "hello_world/hello_world.bin"
         ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
-                    "tests/1.bin"
+                    "tests/3.bin"
         #ram_fname = "/tmp/test.bin"
         #ram_fname = None
 
@@ -308,8 +308,8 @@ class LibreSoCSim(SoCSDRAM):
         )
 
         if cpu == "libresoc":
-            self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12600))
-            #self.comb += active_dbg_cr.eq(1)
+            #self.comb += active_dbg_cr.eq((0x10300 <= pc) & (pc <= 0x12600))
+            self.comb += active_dbg_cr.eq(0)
 
             # get the CR
             self.sync += If(active_dbg_cr & (dmicount == 16),