if nmigen.sim.pysim import fails use nmigen.back.pysim

diff --git a/src/soc/fu/div/test/test_fsm.py b/src/soc/fu/div/test/test_fsm.py
index 75f606fc407aded95a1a5deea1f4e24269afa0fd..fc66d148366aabbb4b7b578b81698e357d56b216 100644 (file)
--- a/src/soc/fu/div/test/test_fsm.py
+++ b/src/soc/fu/div/test/test_fsm.py
@@ -2,7 +2,10 @@ import unittest
 from soc.fu.div.fsm import DivState, DivStateInit, DivStateNext
 from nmigen import Elaboratable, Module, Signal, unsigned
 from nmigen.cli import rtlil
-from nmigen.sim.pysim import Simulator, Delay, Tick
+try:
+    from nmigen.sim.pysim import Simulator, Delay, Tick
+except ImportError:
+    from nmigen.back.pysim import Simulator, Delay, Tick
 
 
 class CheckEvent(Elaboratable):