start adding hazard vector setting in core (unfinished)

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 8082976116f7796346d78236d834ccab8ced5afb..6a8f3e81488fa5fc2c32f8404e440408a5e98a57 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -550,6 +550,15 @@ class NonProductionCore(ControlBase):
                       dest.shape(), wport.i_data.shape())
                 wsigs.append(fu_dest_latch)
 
+                # now connect up the bitvector write hazard
+                if not self.make_hazard_vecs:
+                    continue
+                wv = regs.wv[regfile.lower()]
+                wvport = wv.w_ports[rpidx]
+                comb += wvport.i_data.eq(1) # always enable, for now
+                print ("write vector", regfile, wvport)
+                #if rfile.unary:
+
         # here is where we create the Write Broadcast Bus. simple, eh?
         comb += wport.i_data.eq(ortreereduce_sig(wsigs))
         if rfile.unary: