use same write_vcd for cxxsim as pysim

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index b2233ca85a039259ad8bc59482ecabced27b3fcf..a8a62f1c33efbe779d7bb62a60946160e00c946f 100644 (file)
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -248,12 +248,8 @@ class TestRunner(FHDLTestCase):
                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)
 
         sim.add_sync_process(process)
-        if cxxsim:
-             sim.run()
-        else:
-            with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw",
-                                traces=[]):
-                sim.run()
+        sim.write_vcd("alu_simulator.vcd")
+        sim.run()
 
     def check_alu_outputs(self, alu, dec2, sim, code):