Signal the simulator when completing a VL loop

When we reach the end of the VL loop, by skipping masked bits in the
predicate, we still need to synchronize with the Simulator, even if no
instruction was issued.

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 8d9bec5e3c3eecef309eda699f08ba6c7364fa35..075655f13e3af950dea0fc46da2e5bafcdff0be0 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -628,6 +628,8 @@ class TestIssuerInternal(Elaboratable):
                             comb += new_svstate.srcstep.eq(0)
                             comb += new_svstate.dststep.eq(0)
                             comb += update_svstate.eq(1)
+                            # synchronize with the simulator
+                            comb += self.insn_done.eq(1)
                             # go back to Issue
                             m.next = "ISSUE_START"
                         with m.Else():