Fix some typos and whitespace

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index edb514f82f4b2ec6b31352810b0961cceb4c1905..fb9fbb28fc5b531834cf849c135a44a9daf09531 100644 (file)
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -420,9 +420,8 @@ def test_compunit_fsm():
                 'n_data_o[7:0]', 'n_valid_o', 'n_ready_i']),
         ]),
         ('debug', {'module': 'top'},
                 'n_data_o[7:0]', 'n_valid_o', 'n_ready_i']),
         ]),
         ('debug', {'module': 'top'},

-         ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])
+            ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]

 
 

-    ]

     write_gtkw(
         "test_compunit_fsm1.gtkw",
         "test_compunit_fsm1.vcd",
     write_gtkw(
         "test_compunit_fsm1.gtkw",
         "test_compunit_fsm1.vcd",


@@ -692,10 +691,8 @@ class CompUnitParallelTest:
 def test_compunit_regspec2_fsm():
 
     inspec = [('INT', 'data', '0:15'),
 def test_compunit_regspec2_fsm():
 
     inspec = [('INT', 'data', '0:15'),

-              ('INT', 'shift', '0:15'),
-              ]
-    outspec = [('INT', 'data', '0:15'),
-               ]
+              ('INT', 'shift', '0:15')]
+    outspec = [('INT', 'data', '0:15')]

 
     regspec = (inspec, outspec)
 
 
     regspec = (inspec, outspec)
 


@@ -765,8 +762,7 @@ def test_compunit_regspec3():
     inspec = [('INT', 'a', '0:15'),
               ('INT', 'b', '0:15'),
               ('INT', 'c', '0:15')]
     inspec = [('INT', 'a', '0:15'),
               ('INT', 'b', '0:15'),
               ('INT', 'c', '0:15')]

-    outspec = [('INT', 'o', '0:15'),
-               ]
+    outspec = [('INT', 'o', '0:15')]

 
     regspec = (inspec, outspec)
 
 
     regspec = (inspec, outspec)
 


@@ -800,7 +796,7 @@ def test_compunit_regspec1():
             ('oper_i_None__insn_type', {'display': 'insn_type'}),
             ('oper_i_None__invert_in', {'display': 'invert_in'}),
             ('oper_i_None__imm_data__data[63:0]', {'display': 'data[63:0]'}),
             ('oper_i_None__insn_type', {'display': 'insn_type'}),
             ('oper_i_None__invert_in', {'display': 'invert_in'}),
             ('oper_i_None__imm_data__data[63:0]', {'display': 'data[63:0]'}),

-            ('oper_i_None__imm_data__imm_ok', {'display': 'imm_ok'}),
+            ('oper_i_None__imm_data__ok', {'display': 'imm_ok'}),

             ('oper_i_None__zero_a', {'display': 'zero_a'})]),
         ('operand 1 port', 'in', [
             ('cu_rd__rel_o[1:0]', {'bit': 1}),
             ('oper_i_None__zero_a', {'display': 'zero_a'})]),
         ('operand 1 port', 'in', [
             ('cu_rd__rel_o[1:0]', {'bit': 1}),


@@ -814,7 +810,7 @@ def test_compunit_regspec1():
             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
         ('alu', {'module': 'top.cu.alu'}, [
             ('prev port', 'in', [
             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
         ('alu', {'module': 'top.cu.alu'}, [
             ('prev port', 'in', [

-                'op__insn_type', 'op__invert_i', 'a[15:0]', 'b[15:0]',
+                'op__insn_type', 'op__invert_in', 'a[15:0]', 'b[15:0]',

                 'valid_i', 'ready_o']),
             ('next port', 'out', [
                 'alu_o[15:0]', 'valid_o', 'ready_i'])]),
                 'valid_i', 'ready_o']),
             ('next port', 'out', [
                 'alu_o[15:0]', 'valid_o', 'ready_i'])]),


@@ -829,8 +825,7 @@ def test_compunit_regspec1():
 
     inspec = [('INT', 'a', '0:15'),
               ('INT', 'b', '0:15')]
 
     inspec = [('INT', 'a', '0:15'),
               ('INT', 'b', '0:15')]

-    outspec = [('INT', 'o', '0:15'),
-               ]
+    outspec = [('INT', 'o', '0:15')]

 
     regspec = (inspec, outspec)
 
 
     regspec = (inspec, outspec)