move sim call before core run in test_core.py

to give PC a chance to settle in regfile

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 14354873e1be3711052cea785bfb4e968078b89a..0c1be1411fa5e357d1356ba29cb9a1287be19f2a 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -278,18 +278,6 @@ class TestRunner(FHDLTestCase):
                         # ask the decoder to decode this binary data (endian'd)
                         yield instruction.eq(ins)          # raw binary instr.
                         yield Settle()
-                        yield core.p.i_valid.eq(1)
-                        yield
-                        o_ready = yield core.p.o_ready
-                        while True:
-                            if o_ready:
-                                break
-                            yield
-                            o_ready = yield core.p.o_ready
-                        yield core.p.i_valid.eq(0)
-
-                        # set operand and get inputs
-                        yield from wait_for_busy_clear(core)
 
                         print("sim", code)
                         # call simulated operation
@@ -306,6 +294,19 @@ class TestRunner(FHDLTestCase):
                         yield stateregs.regs[pc_regnum].reg.eq(pc)
                         yield Settle()
 
+                        yield core.p.i_valid.eq(1)
+                        yield
+                        o_ready = yield core.p.o_ready
+                        while True:
+                            if o_ready:
+                                break
+                            yield
+                            o_ready = yield core.p.o_ready
+                        yield core.p.i_valid.eq(0)
+
+                        # set operand and get inputs
+                        yield from wait_for_busy_clear(core)
+
                         # register check
                         yield from check_regs(self, sim, core, test, code)