litex expects wishbone "err" signals even if not used
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 5 Mar 2021 21:08:28 +0000 (21:08 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 5 Mar 2021 21:08:28 +0000 (21:08 +0000)
src/soc/simple/issuer.py

index 07a460e..72b432d 100644 (file)
@@ -85,7 +85,8 @@ class TestIssuerInternal(Elaboratable):
         if self.sram4x4k:
             self.sram4k = []
             for i in range(4):
-                self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i))
+                self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
+                                                    features={'err'}))
 
         # add interrupt controller?
         self.xics = hasattr(pspec, "xics") and pspec.xics == True