whoops, docstring indentation

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 35becb0166cadc6b22c40a5299e98d293ac7a325..d543203a217f6c0ed17cb8758a95c142f9b0f3db 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -90,11 +90,12 @@ class NonProductionCore(Elaboratable):
         return fu_bitdict
 
     def connect_rdports(self, m, fu_bitdict):
-    """connect read ports
+        """connect read ports
 
-    orders the read regspecs into a dict-of-dicts, by regfile, by regport name,
-    then connects all FUs that want that regport by way of a PriorityPicker.
-    """
+        orders the read regspecs into a dict-of-dicts, by regfile, by
+        regport name, then connects all FUs that want that regport by
+        way of a PriorityPicker.
+        """
         comb, sync = m.d.comb, m.d.sync
         fus = self.fus.fus
         regs = self.regs
@@ -154,15 +155,16 @@ class NonProductionCore(Elaboratable):
                     comb += src.eq(rport.data_o) # all FUs connect to same port
 
     def connect_wrports(self, m, fu_bitdict):
-    """connect write ports
+        """connect write ports
 
-    orders the write regspecs into a dict-of-dicts, by regfile, by regport name,
-    then connects all FUs that want that regport by way of a PriorityPicker.
+        orders the write regspecs into a dict-of-dicts, by regfile,
+        by regport name, then connects all FUs that want that regport
+        by way of a PriorityPicker.
 
-    note that the write-port wen, write-port data, and go_wr_i all need to
-    be on the exact same clock cycle.  as there is a combinatorial loop bug
-    at the moment, these all use sync.
-    """
+        note that the write-port wen, write-port data, and go_wr_i all need to
+        be on the exact same clock cycle.  as there is a combinatorial loop bug
+        at the moment, these all use sync.
+        """
         comb, sync = m.d.comb, m.d.sync
         fus = self.fus.fus
         regs = self.regs