From: Tobias Platen <tplaten@posteo.de>
Date: Mon, 20 Apr 2020 15:23:05 +0000 (+0200)
Subject: testcase fo mulli
X-Git-Tag: div_pipeline~1418
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=076eaaf0f52dcd0f7ffcf74aab7f1365fd9ae240

testcase fo mulli
---

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index f356dd76..0a26380c 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -115,6 +115,13 @@ class DecoderTestCase(FHDLTestCase):
         with Program(lst) as program:
             self.run_tst_program(program, [1])
 
+    def test_mulli(self):
+        lst = ["addi 1, 0, 3",
+               "mulli 1, 1, 2"
+               ]
+        with Program(lst) as program:
+            self.run_tst_program(program, [1])
+
     def run_tst_program(self, prog, reglist):
         simulator = InternalOpSimulator()
         self.run_tst(prog, simulator)