From: Tobias Platen <tplaten@posteo.de>
Date: Thu, 7 Jan 2021 16:50:28 +0000 (+0100)
Subject: mfspr is RT, SPR
X-Git-Tag: 24jan2021_ls180~35
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=179c6f905aa3e5dbfc717604446be78735d719e6

mfspr is RT, SPR
---

diff --git a/src/soc/fu/mmu/test/test_pipe_caller.py b/src/soc/fu/mmu/test/test_pipe_caller.py
index e9410e1f..71aae015 100644
--- a/src/soc/fu/mmu/test/test_pipe_caller.py
+++ b/src/soc/fu/mmu/test/test_pipe_caller.py
@@ -72,18 +72,17 @@ def check_fsm_outputs(fsm, pdecode2, sim, code):
 class MMUTestCase(TestAccumulatorBase):
     # MMU handles MTSPR, MFSPR, DCBZ and TLBIE.
     # other instructions here -> must be load/store
+
+    #before running the test case: set DISR and DAR
+
     def case_mfspr_after_invalid_load(self):
-        lst = [ "lhz 3, 0(1)" , # case 1 load -- test infrastructure needed
-                "mfspr 18, 1", # DSISR to reg 1 -- KeyError: 2 in simulator
-                "mfspr 19, 2", # DAR to reg 2   -- with key = spr_dict[key].SPR
+        lst = [ # TODO -- set SPR on both sinulator and port interface
+                "mfspr 1, 18", # DSISR to reg 1 -- KeyError: 2 in simulator
+                "mfspr 2, 19", # DAR to reg 2   -- with key = spr_dict[key].SPR
                 # TODO -- verify returned sprvals
               ]
 
         initial_regs = [0] * 32
-        initial_regs[1] = 0xBADCAB1E
-        initial_regs[2] = 0xDEADC0DE
-        initial_regs[5] = 0x100
-        initial_regs[6] = 0x100
 
         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
                         'XER': 0xe00c0000}