From: Cesar Strauss <cestrauss@gmail.com>
Date: Fri, 1 Jan 2021 21:05:38 +0000 (-0300)
Subject: Add zero CR test case and fix comments
X-Git-Tag: 24jan2021_ls180~39
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=1c274daab0955fa0e1cb98c4fe43709b7f795c99

Add zero CR test case and fix comments
---

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 76d8e221..7aecaf69 100644
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -585,6 +585,8 @@ def test_alu_parallel():
         yield from send(0x80, 2, MicrOp.OP_EXTS, rc=1)
         # sign extend -128 (8 bits)
         yield from send(2, 0x80, MicrOp.OP_EXTSWSLI)
+        # 5 - 5
+        yield from send(5, 5, MicrOp.OP_CMP, rc=1)
 
     def consumer():
         # receive and check results, interspersed with wait states
@@ -595,11 +597,13 @@ def test_alu_parallel():
         result = yield from receive()
         assert result[0] == 8
         # 2 * 3 = 6
+        # 6 > 0 => CR = 0b100
         result = yield from receive()
         assert result == (6, 0b100)
         yield
         yield
         # (-6) + 3 = -3
+        # -3 < 0 => CR = 0b010
         result = yield from receive()
         assert result == (65533, 0b010)  # unsigned equivalent to -2
         # 5 - 3 = 2
@@ -619,11 +623,16 @@ def test_alu_parallel():
         result = yield from receive()
         assert result[0] == 13
         # sign extend -128 (8 bits) = -128 (16 bits)
+        # -128 < 0 => CR = 0b010
         result = yield from receive()
         assert result == (0xFF80, 0b010)
         # sign extend -128 (8 bits) = -128 (16 bits)
         result = yield from receive()
         assert result[0] == 0xFF80
+        # 5 - 5 = 0
+        # 0 == 0 => CR = 0b001
+        result = yield from receive()
+        assert result == (0, 0b001)
 
     sim.add_sync_process(producer)
     sim.add_sync_process(consumer)
@@ -647,7 +656,7 @@ def write_alu_gtkw(gtkw_name, clk_period=1e-6, sub_module=None,
         'ready_i',
         'alu_o[15:0]',
         'alu_o_ok',
-        'alu_cr[2:0]',
+        'alu_cr[15:0]',
         'alu_cr_ok'
     ]
     # determine the module name of the DUT
diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index eac4d779..95482721 100644
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -489,7 +489,7 @@ def scoreboard_sim(op):
                         rc=1, rdmaskn=[0, 1],
                         src_delays=[2, 1], dest_delays=[0, 2])
     # 5 - 5 = 0
-    # 0 == 0 => CR = 0b000
+    # 0 == 0 => CR = 0b001
     yield from op.issue([5, 2], MicrOp.OP_CMP, [0, 0b001],
                         imm=5, imm_ok=1, rc=1,
                         src_delays=[0, 1], dest_delays=[2, 1])