From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 15 May 2020 13:19:53 +0000 (+0100)
Subject: add count leading zero test into logical test_pipe_caller.py
X-Git-Tag: div_pipeline~1202
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=2fcb3fde530f101374fea8cae62fb8c135243fb0

add count leading zero test into logical test_pipe_caller.py
---

diff --git a/src/soc/logical/test/test_pipe_caller.py b/src/soc/logical/test/test_pipe_caller.py
index 9fd92cc3..76f93a54 100644
--- a/src/soc/logical/test/test_pipe_caller.py
+++ b/src/soc/logical/test/test_pipe_caller.py
@@ -123,6 +123,16 @@ class LogicalTestCase(FHDLTestCase):
             initial_regs[1] = random.randint(0, (1<<64)-1)
             self.run_tst_program(Program(lst), initial_regs)
 
+    def test_cntz(self):
+        insns = ["cntlzd", "cnttzd"]
+        for i in range(10):
+            choice = random.choice(insns)
+            lst = [f"{choice} 3, 1"]
+            print(lst)
+            initial_regs = [0] * 32
+            initial_regs[1] = random.randint(0, (1<<64)-1)
+            self.run_tst_program(Program(lst), initial_regs)
+
     def test_parity(self):
         insns = ["prtyw", "prtyd"]
         for i in range(10):