From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 15 Oct 2020 17:11:11 +0000 (+0100)
Subject: wrong pspec variable in selecting pll clock
X-Git-Tag: 24jan2021_ls180~145
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=3947809e309f4aa930f9be90bc40f951b348053a

wrong pspec variable in selecting pll clock
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 0d1fa1f2..ae6c24bf 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -453,7 +453,7 @@ class TestIssuer(Elaboratable):
         self.clksel = ClockSelect()
 
         # PLL direct clock or not
-        self.pll_en = hasattr(pspec, "use_pll") and pspec.pll_en
+        self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 
     def elaborate(self, platform):
         m = Module()