From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 3 Dec 2020 15:34:33 +0000 (+0000)
Subject: add 3 more 4k SRAMs, change WB bus width to 64 in ls180 litex
X-Git-Tag: 24jan2021_ls180~77
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=3a2999107797c8ffb756126797bfb8c868eb93de;hp=041affe55388ff708be4950e6ca847b21a55143b

add 3 more 4k SRAMs, change WB bus width to 64 in ls180 litex
---

diff --git a/src/soc/litex/florent/Makefile b/src/soc/litex/florent/Makefile
index 754d5d08..d1c5cc1d 100644
--- a/src/soc/litex/florent/Makefile
+++ b/src/soc/litex/florent/Makefile
@@ -2,6 +2,9 @@ ls180:
 	./ls180soc.py --build --platform=ls180
 	cp build/ls180/gateware/ls180.v .
 	cp build/ls180/gateware/mem.init .
+	cp build/ls180/gateware/mem_1.init .
+	cp build/ls180/gateware/mem_2.init .
+	cp build/ls180/gateware/mem_3.init .
 	cp libresoc/libresoc.v .
 	yosys -p 'read_verilog libresoc.v' \
           -p 'write_ilang libresoc_cvt.il'
diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index eb2afafb..8566988a 100755
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -319,13 +319,16 @@ class LibreSoCSim(SoCCore):
 
         self.mem_map["main_ram"] = 0x90000000
         self.mem_map["sram"] = 0x00000000
+        self.mem_map["sram1"] = 0x00001000
+        self.mem_map["sram2"] = 0x00002000
+        self.mem_map["sram3"] = 0x00003000
 
         # SoCCore -------------------------------------------------------------
         SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
             cpu_type                 = "microwatt",
             cpu_cls                  = LibreSoC   if cpu == "libresoc" \
                                        else Microwatt,
-            #bus_data_width           = 64,
+            bus_data_width           = 64,
             csr_address_width        = 14, # limit to 0x8000
             cpu_variant              = variant,
             csr_data_width            = 8,
@@ -336,13 +339,18 @@ class LibreSoCSim(SoCCore):
             sdram_module          = sdram_module,
             sdram_data_width      = sdram_data_width,
             integrated_rom_size      = 0, # if ram_fname else 0x10000,
-            integrated_sram_size     = 0x200,
+            integrated_sram_size     = 0x1000,
             #integrated_main_ram_init  = ram_init,
             integrated_main_ram_size = 0x00000000 if with_sdram \
                                         else 0x10000000 , # 256MB
             )
         self.platform.name = "ls180"
 
+        # add 3 more 4k integrated SRAMs
+        self.add_ram("sram1", self.mem_map["sram1"], 0x1000)
+        self.add_ram("sram2", self.mem_map["sram2"], 0x1000)
+        self.add_ram("sram3", self.mem_map["sram3"], 0x1000)
+
         # SDR SDRAM ----------------------------------------------
         if False: # not self.integrated_main_ram_size:
             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))