From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sun, 5 Apr 2020 17:59:40 +0000 (-0400)
Subject: Add class for combining multiple instruction classes
X-Git-Tag: div_pipeline~1482
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=5c97b5ef4bce2eb475319d43f0791b6e77ba1cb5

Add class for combining multiple instruction classes
---

diff --git a/src/soc/decoder/isa/__init__.py b/src/soc/decoder/isa/__init__.py
index e69de29b..8f5f9f2a 100644
--- a/src/soc/decoder/isa/__init__.py
+++ b/src/soc/decoder/isa/__init__.py
@@ -0,0 +1,6 @@
+from fixedarith import fixedarith
+from fixedload import fixedload
+
+
+class ISA(fixedarith, fixedload):
+    pass
diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py
index b1a90de3..73692f00 100644
--- a/src/soc/decoder/isa/test_caller.py
+++ b/src/soc/decoder/isa/test_caller.py
@@ -6,33 +6,10 @@ from soc.decoder.isa.caller import ISACaller
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
 from soc.simulator.program import Program
-from soc.simulator.qemu import run_program
 from soc.decoder.isa.caller import ISACaller, inject
-from soc.decoder.helpers import (EXTS64, EXTZ64, ROTL64, ROTL32, MASK,)
 from soc.decoder.selectable_int import SelectableInt
-from soc.decoder.selectable_int import selectconcat as concat
 from soc.decoder.orderedset import OrderedSet
-
-class fixedarith(ISACaller):
-
-    @inject()
-    def op_addi(self, RA):
-        if RA == 0:
-            RT = SI
-        else:
-            RT = RA + SI
-        return (RT,)
-    @inject()
-    def op_add(self, RA, RB):
-        RT = RA + RB
-        return (RT,)
-
-    instrs = {}
-    instrs['addi'] = (op_addi, OrderedSet(['RA']),
-                OrderedSet(), OrderedSet(['RT']))
-    instrs['add'] = (op_add, OrderedSet(['RA', 'RB']),
-                OrderedSet(), OrderedSet(['RT']))
-
+from soc.decoder.isa import ISA
 
 
 class Register:
@@ -48,7 +25,7 @@ class DecoderTestCase(FHDLTestCase):
         instruction = Signal(32)
 
         pdecode = create_pdecode()
-        simulator = fixedarith(pdecode, initial_regs)
+        simulator = ISA(pdecode, initial_regs)
 
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)