From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 3 Nov 2020 13:53:41 +0000 (+0000)
Subject: swap jtag pinorder to match ulx3s
X-Git-Tag: 24jan2021_ls180~117
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=68d125f3ccf46722792d7f56cf55861ec70759fd

swap jtag pinorder to match ulx3s
---

diff --git a/src/soc/litex/florent/versa_ecp5.py b/src/soc/litex/florent/versa_ecp5.py
index 75e33bc2..464e9412 100755
--- a/src/soc/litex/florent/versa_ecp5.py
+++ b/src/soc/litex/florent/versa_ecp5.py
@@ -43,9 +43,9 @@ class VersaECP5TestSoC(versa_ecp5.BaseSoC):
         # define the pins, add as an extension, *then* request it
         jtag_ios = [
             ("jtag", 0,
-                Subsignal("tck", Pins("B19"), IOStandard("LVCMOS25")),
+                Subsignal("tdi", Pins("B19"), IOStandard("LVCMOS25")),
                 Subsignal("tms", Pins("B12"), IOStandard("LVCMOS25")),
-                Subsignal("tdi", Pins("B9"), IOStandard("LVCMOS25")),
+                Subsignal("tck", Pins("B9"), IOStandard("LVCMOS25")),
                 Subsignal("tdo", Pins("E6"), IOStandard("LVCMOS25")),
             )
         ]