From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 4 Aug 2020 16:56:12 +0000 (+0100)
Subject: tracked down byte-reversal in LDST ISACaller and LDSTCompUnit
X-Git-Tag: semi_working_ecp5~447
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=78c7d5afe07c47d6d88dde38611cfd421f6b44d5

tracked down byte-reversal in LDST ISACaller and LDSTCompUnit
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 8c5ec68e..c8b5f4de 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -131,13 +131,13 @@ class Mem:
         print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
 
     def __call__(self, addr, sz):
-        val = self.ld(addr.value, sz)
+        val = self.ld(addr.value, sz, swap=False)
         print("memread", addr, sz, val)
         return SelectableInt(val, sz*8)
 
     def memassign(self, addr, sz, val):
         print("memassign", addr, sz, val)
-        self.st(addr.value, val.value, sz)
+        self.st(addr.value, val.value, sz, swap=False)
 
 
 class GPR(dict):
diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 4e34a769..e464da2a 100644
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -483,7 +483,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         comb += addr_ok.eq(self.pi.addr_ok_o)  # no exc, address fine
 
         # byte-reverse on LD - yes this is inverted
-        with m.If(self.oper_i.byte_reverse):
+        with m.If(~self.oper_i.byte_reverse):
             comb += ldd_o.eq(pi.ld.data)  # put data out, straight (as BE)
         with m.Else():
             # byte-reverse the data based on ld/st width (turn it to LE)
@@ -494,7 +494,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         comb += ld_ok.eq(pi.ld.ok)  # ld.ok *closes* (freezes) ld data
 
         # yes this also looks odd (inverted)
-        with m.If(self.oper_i.byte_reverse):
+        with m.If(~self.oper_i.byte_reverse):
             comb += pi.st.data.eq(srl[2])  # 3rd operand latch
         with m.Else():
             # byte-reverse the data based on width
diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index 0b85ca74..63cb5d10 100644
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -96,7 +96,7 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3, 4])
 
-    @unittest.skip("disable")
+    #@unittest.skip("disable")
     def test_ldst(self):
         lst = ["addi 1, 0, 0x5678",
                "addi 2, 0, 0x1234",
@@ -111,6 +111,21 @@ class GeneralTestCases(FHDLTestCase):
                                  [1, 2, 3],
                                  initial_mem)
 
+    #@unittest.skip("disable")
+    def test_ldst_update(self):
+        lst = ["addi 1, 0, 0x5678",
+               "addi 2, 0, 0x1234",
+               "stwu  1, 0(2)",
+               "lwz  3, 0(2)"
+               ]
+        initial_mem = {0x1230: (0x5432123412345678, 8),
+                       0x1238: (0xabcdef0187654321, 8),
+                       }
+        with Program(lst, bigendian) as program:
+            self.run_tst_program(program,
+                                 [1, 2, 3],
+                                 initial_mem)
+
     @unittest.skip("disable")
     def test_ld_rev_ext(self):
         lst = ["addi 1, 0, 0x5678",
@@ -131,7 +146,7 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
-    @unittest.skip("disable")
+    #@unittest.skip("disable")
     def test_ldst_extended(self):
         lst = ["addi 1, 0, 0x5678",
                "addi 2, 0, 0x1234",
@@ -254,6 +269,7 @@ class GeneralTestCases(FHDLTestCase):
             program.assembly = '\n'.join(disassembly) + '\n' # XXX HACK!
             self.run_tst_program(program, [1, 3])
 
+    @unittest.skip("disable")
     def test_loop(self):
         """in godbolt.org:
         register unsigned long i asm ("r12");
@@ -272,6 +288,7 @@ class GeneralTestCases(FHDLTestCase):
         with Program(lst, bigendian) as program:
             self.run_tst_program(program, [9], initial_mem={})
 
+    @unittest.skip("disable")
     def test_30_addis(self):
         lst = [  # "addi 0, 0, 5",
             "addis 12, 0, 0",