From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 8 Oct 2020 12:47:42 +0000 (+0100)
Subject: rework jtag test to use JTAG class not DMITAP
X-Git-Tag: 24jan2021_ls180~189
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=8e5df9cc934a61de8c942430d981bd45cbf45f8e

rework jtag test to use JTAG class not DMITAP
---

diff --git a/src/soc/debug/jtag.py b/src/soc/debug/jtag.py
index c7c96454..2a9507a1 100644
--- a/src/soc/debug/jtag.py
+++ b/src/soc/debug/jtag.py
@@ -60,7 +60,7 @@ class Pins:
 
 
 class JTAG(DMITAP, Pins):
-    def __init__(self, pinset):
+    def __init__(self, pinset, wb_data_wid=64):
         DMITAP.__init__(self, ir_width=4)
         Pins.__init__(self, pinset)
 
@@ -77,7 +77,7 @@ class JTAG(DMITAP, Pins):
 
         # create and connect wishbone 
         self.wb = self.add_wishbone(ircodes=[5, 6, 7],
-                                   address_width=29, data_width=64,
+                                   address_width=29, data_width=wb_data_wid,
                                    name="jtag_wb")
 
         # create DMI2JTAG (goes through to dmi_sim())
diff --git a/src/soc/debug/jtagutils.py b/src/soc/debug/jtagutils.py
index 1dee686c..f0b1830d 100644
--- a/src/soc/debug/jtagutils.py
+++ b/src/soc/debug/jtagutils.py
@@ -41,7 +41,7 @@ def tms_data_getset(dut, tms, d_len, d_in=0):
         tdi = 1 if (d_in & (1<<i)) else 0
         yield dut.cbus.tck.eq(1)
         yield from client_sync(dut)
-        res |= (1<<i) if (yield dut.bus.tdo) else 0
+        res |= (1<<i) if (yield dut.cbus.tdo) else 0
         yield
         yield from client_sync(dut)
         yield dut.cbus.tdi.eq(tdi)
@@ -98,7 +98,7 @@ def jtag_srv(dut):
         yield dut.bus.tms.eq(tms)
         yield dut.bus.tdi.eq(tdi)
         yield
-
+    print ("jtag srv stopping")
 
 
 def get_data(s, length=1024, timeout=None):
diff --git a/src/soc/debug/test/dmi_sim.py b/src/soc/debug/test/dmi_sim.py
index c0d376dd..66d544d1 100644
--- a/src/soc/debug/test/dmi_sim.py
+++ b/src/soc/debug/test/dmi_sim.py
@@ -43,3 +43,4 @@ def dmi_sim(dut):
             yield
             yield dmi.ack_o.eq(0)
 
+    print ("dmi sim stopping")
diff --git a/src/soc/debug/test/test_jtag_tap_srv.py b/src/soc/debug/test/test_jtag_tap_srv.py
index 45b4ffb9..597eb0a6 100644
--- a/src/soc/debug/test/test_jtag_tap_srv.py
+++ b/src/soc/debug/test/test_jtag_tap_srv.py
@@ -9,7 +9,7 @@ from c4m.nmigen.jtag.tap import TAP, IOType
 from c4m.nmigen.jtag.bus import Interface as JTAGInterface
 from soc.debug.dmi import DMIInterface, DBGCore
 from soc.debug.test.dmi_sim import dmi_sim
-from soc.debug.dmi2jtag import DMITAP
+from soc.debug.jtag import JTAG, dummy_pinset
 from soc.debug.test.jtagremote import JTAGServer, JTAGClient
 
 from nmigen_soc.wishbone.sram import SRAM
@@ -31,7 +31,7 @@ WB_READ = 6
 WB_WRRD = 7
 
 
-def jtag_sim(dut):
+def jtag_sim(dut, srv_dut):
 
     ####### JTAGy stuff (IDCODE) ######
 
@@ -78,64 +78,57 @@ def jtag_sim(dut):
     ####### JTAG to Wishbone ######
 
     # write Wishbone address
-    yield from jtag_read_write_reg(dut, WB_ADDR, 16, 0x18)
+    yield from jtag_read_write_reg(dut, WB_ADDR, 64, 0x18)
 
     # write/read wishbone data
-    data = yield from jtag_read_write_reg(dut, WB_WRRD, 16, 0xfeef)
+    data = yield from jtag_read_write_reg(dut, WB_WRRD, 64, 0xfeef)
     print ("wb write", hex(data))
 
     # write Wishbone address
-    yield from jtag_read_write_reg(dut, WB_ADDR, 16, 0x18)
+    yield from jtag_read_write_reg(dut, WB_ADDR, 64, 0x18)
 
     # write/read wishbone data
-    data = yield from jtag_read_write_reg(dut, WB_READ, 16, 0)
+    data = yield from jtag_read_write_reg(dut, WB_READ, 64, 0)
     print ("wb read", hex(data))
 
     ####### done - tell dmi_sim to stop (otherwise it won't) ########
 
-    dut.stop = True
+    srv_dut.stop = True
+    print ("jtag sim stopping")
 
 
 if __name__ == '__main__':
-    dut = DMITAP(ir_width=4)
+    dut = JTAG(dummy_pinset(), wb_data_wid=64)
     dut.stop = False
 
+    # rather than the client access the JTAG bus directly
+    # create an alternative that the client sets
+    class Dummy: pass
+    cdut = Dummy()
+    cdut.cbus = JTAGInterface()
+    cdut._ir_width = 4
+
     # set up client-server on port 44843-something
     dut.s = JTAGServer()
     if len(sys.argv) != 2 or sys.argv[1] != 'server':
-        dut.c = JTAGClient()
+        cdut.c = JTAGClient()
         dut.s.get_connection()
     else:
         dut.s.get_connection(None) # block waiting for connection
 
-    # rather than the client access the JTAG bus directly
-    # create an alternative that the client sets
-    dut.cbus = JTAGInterface()
-
-    iotypes = (IOType.In, IOType.Out, IOType.TriOut, IOType.InTriOut)
-    ios = [dut.add_io(iotype=iotype) for iotype in iotypes]
-    dut.sr = dut.add_shiftreg(ircode=4, length=3) # test loopback register
-
-    # create and connect wishbone SRAM (a quick way to do WB test)
-    dut.wb = dut.add_wishbone(ircodes=[WB_ADDR, WB_READ, WB_WRRD],
-                               address_width=16, data_width=16)
-    memory = Memory(width=16, depth=16)
+    memory = Memory(width=64, depth=16)
     sram = SRAM(memory=memory, bus=dut.wb)
 
-    # create DMI2JTAG (goes through to dmi_sim())
-    dut.dmi = dut.add_dmi(ircodes=[DMI_ADDR, DMI_READ, DMI_WRRD])
-
     m = Module()
     m.submodules.ast = dut
     m.submodules.sram = sram
-    m.d.comb += dut.sr.i.eq(dut.sr.o) # loopback
 
     sim = Simulator(m)
     sim.add_clock(1e-6, domain="sync")      # standard clock
 
     sim.add_sync_process(wrap(jtag_srv(dut))) # jtag server
     if len(sys.argv) != 2 or sys.argv[1] != 'server':
-        sim.add_sync_process(wrap(jtag_sim(dut))) # actual jtag tester
+        sim.add_sync_process(wrap(jtag_sim(cdut, dut))) # actual jtag tester
     else:
         print ("running server only as requested, use openocd remote to test")
     sim.add_sync_process(wrap(dmi_sim(dut)))  # handles (pretends to be) DMI