From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 1 Jun 2020 21:39:06 +0000 (+0100)
Subject: okaaay add a "rdflags" function which obtains the yes/no flags for each register... 
X-Git-Tag: div_pipeline~663
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=93fb5e930101a3bbb317e6180fc598f56b43cb9c

okaaay add a "rdflags" function which obtains the yes/no flags for each register to the CompUnit
this to be used by the Decode phase
---

diff --git a/libreriscv b/libreriscv
index 6a79599c..041f868b 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 6a79599c792e9271203c29082ee512a46930be85
+Subproject commit 041f868b620685068f375bce39c3aacf6aa986c4
diff --git a/src/soc/fu/alu/pipe_data.py b/src/soc/fu/alu/pipe_data.py
index cdd5c97a..33f54b02 100644
--- a/src/soc/fu/alu/pipe_data.py
+++ b/src/soc/fu/alu/pipe_data.py
@@ -1,4 +1,4 @@
-from nmigen import Signal, Const
+from nmigen import Signal, Const, Cat
 from soc.fu.alu.alu_input_record import CompALUOpSubset
 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
 from ieee754.fpcommon.getop import FPPipeContext
@@ -64,3 +64,7 @@ class ALUOutputData(IntegerData):
 class ALUPipeSpec(CommonPipeSpec):
     regspec = (ALUInputData.regspec, ALUOutputData.regspec)
     opsubsetkls = CompALUOpSubset
+    def rdflags(self, e): # in order of regspec
+        reg1_ok = e.read_reg1.ok # RA
+        reg2_ok = e.read_reg2.ok # RB
+        return Cat(reg1_ok, reg2_ok, 1, 1) # RA RB CA SO
diff --git a/src/soc/fu/alu/pipeline.py b/src/soc/fu/alu/pipeline.py
index 3a065b2e..a84efe1e 100644
--- a/src/soc/fu/alu/pipeline.py
+++ b/src/soc/fu/alu/pipeline.py
@@ -15,6 +15,7 @@ class ALUStages(PipeModBaseChain):
 class ALUBasePipe(ControlBase):
     def __init__(self, pspec):
         ControlBase.__init__(self)
+        self.pspec = pspec
         self.pipe1 = ALUStages(pspec)
         self._eqs = self.connect([self.pipe1])
 
diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index 4af59f34..a71c9dd1 100644
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -23,7 +23,7 @@
     op_bctarl  CR, TAR,   CTR
 """
 
-from nmigen import Signal, Const
+from nmigen import Signal, Const, Cat
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.decoder.power_decoder2 import Data
 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
@@ -92,3 +92,8 @@ class BranchOutputData(IntegerData):
 class BranchPipeSpec(CommonPipeSpec):
     regspec = (BranchInputData.regspec, BranchOutputData.regspec)
     opsubsetkls = CompBROpSubset
+    def rdflags(self, e): # in order of regspec
+        cr1_en = e.read_cr1.ok # CR A
+        spr1_ok = e.read_spr1.ok # SPR1
+        spr2_ok = e.read_spr2.ok # SPR2
+        return Cat(spr1_ok, spr2_ok, cr1_en, 1) # CIA CR SPR1 SPR2
diff --git a/src/soc/fu/branch/pipeline.py b/src/soc/fu/branch/pipeline.py
index 545b3435..1cdb3e9a 100644
--- a/src/soc/fu/branch/pipeline.py
+++ b/src/soc/fu/branch/pipeline.py
@@ -11,6 +11,7 @@ class BranchStages(PipeModBaseChain):
 class BranchBasePipe(ControlBase):
     def __init__(self, pspec):
         ControlBase.__init__(self)
+        self.pspec = pspec
         self.pipe1 = BranchStages(pspec)
         self._eqs = self.connect([self.pipe1])
 
diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index d40549d5..203055ad 100644
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -40,6 +40,7 @@ see:
 
 """
 
+from nmigen import Cat
 from nmigen.cli import rtlil
 from soc.experiment.compalu_multi import MultiCompUnit
 
@@ -78,6 +79,10 @@ class FunctionUnitBaseSingle(MultiCompUnit):
     note that it is through MultiCompUnit.get_in/out that we *actually*
     connect up the association between regspec variable names (defined
     in the pipe_data).
+
+    note that the rdflags function obtains (dynamically, from instruction
+    decoding) which read-register ports are to be requested.  this is not
+    ideal (it could be a lot neater) but works for now.
     """
     def __init__(self, speckls, pipekls):
         pspec = speckls(id_wid=2)                # spec (NNNPipeSpec instance)
@@ -86,6 +91,10 @@ class FunctionUnitBaseSingle(MultiCompUnit):
         alu = pipekls(pspec)                     # create actual NNNBasePipe
         super().__init__(regspec, alu, opsubset) # pass to MultiCompUnit
 
+    def rdflags(self, e):
+        print (dir(self.alu))
+        return self.alu.pspec.rdflags(e)
+
 
 ##############################################################
 # TODO: ReservationStations-based (FunctionUnitBaseConcurrent)
@@ -112,6 +121,7 @@ class BranchFunctionUnit(FunctionUnitBaseSingle):
 class ShiftRotFunctionUnit(FunctionUnitBaseSingle):
     def __init__(self): super().__init__(ShiftRotPipeSpec, ShiftRotBasePipe)
 
+
 #####################################################################
 ###### actual Function Units: these are "multi" stage pipelines #####
 
diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 08a704dc..605b9127 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -96,13 +96,6 @@ def get_inp_indexed(cu, inp):
             res[i] = inp[wrop]
     return res
 
-def get_cu_rd_mask(n_src, inp):
-    mask = 0
-    for i in range(n_src):
-        if i in inp:
-            mask |= (1<<i)
-    return mask
-
 
 class TestRunner(FHDLTestCase):
     def __init__(self, test_data, fukls, iodef, funit):
@@ -160,7 +153,7 @@ class TestRunner(FHDLTestCase):
                     inp = get_inp_indexed(cu, iname)
 
                     # reset read-operand mask
-                    rdmask = get_cu_rd_mask(cu.n_src, inp)
+                    rdmask = cu.rdflags(pdecode2.e)
                     yield cu.rdmaskn.eq(~rdmask)
 
                     # reset write-operand mask
diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index c22a3b1e..b16e5688 100644
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -2,7 +2,7 @@
 Links:
 * https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
 """
-from nmigen import Signal, Const
+from nmigen import Signal, Const, Cat
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
 from soc.fu.cr.cr_input_record import CompCROpSubset
@@ -70,3 +70,11 @@ class CROutputData(IntegerData):
 class CRPipeSpec(CommonPipeSpec):
     regspec = (CRInputData.regspec, CROutputData.regspec)
     opsubsetkls = CompCROpSubset
+    def rdflags(self, e): # in order of regspec
+        reg1_ok = e.read_reg1.ok # RA/RC
+        reg2_ok = e.read_reg2.ok # RB
+        full_reg = e.read_cr_whole # full CR
+        cr1_en = e.read_cr1.ok # CR A
+        cr2_en = e.read_cr2.ok # CR B
+        cr3_en = e.read_cr3.ok # CR C
+        return Cat(reg1_ok, reg2_ok, full_reg, cr1_en, cr2_en, cr3_en)
diff --git a/src/soc/fu/cr/pipeline.py b/src/soc/fu/cr/pipeline.py
index 050d0244..af756eb1 100644
--- a/src/soc/fu/cr/pipeline.py
+++ b/src/soc/fu/cr/pipeline.py
@@ -11,6 +11,7 @@ class CRStages(PipeModBaseChain):
 class CRBasePipe(ControlBase):
     def __init__(self, pspec):
         ControlBase.__init__(self)
+        self.pspec = pspec
         self.pipe1 = CRStages(pspec)
         self._eqs = self.connect([self.pipe1])
 
diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index 86e03622..ba24ce6d 100644
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -1,4 +1,4 @@
-from nmigen import Signal, Const
+from nmigen import Signal, Const, Cat
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.fu.pipe_data import IntegerData
 from soc.decoder.power_decoder2 import Data
@@ -54,3 +54,7 @@ class LogicalOutputData(IntegerData):
 class LogicalPipeSpec(CommonPipeSpec):
     regspec = (LogicalInputData.regspec, LogicalOutputData.regspec)
     opsubsetkls = CompLogicalOpSubset
+    def rdflags(self, e): # in order of regspec
+        reg1_ok = e.read_reg1.ok # RA
+        reg2_ok = e.read_reg2.ok # RB
+        return Cat(reg1_ok, reg2_ok) # RA RB
diff --git a/src/soc/fu/logical/pipeline.py b/src/soc/fu/logical/pipeline.py
index 4ae1d1d4..41aea148 100644
--- a/src/soc/fu/logical/pipeline.py
+++ b/src/soc/fu/logical/pipeline.py
@@ -15,6 +15,7 @@ class LogicalStages(PipeModBaseChain):
 class LogicalBasePipe(ControlBase):
     def __init__(self, pspec):
         ControlBase.__init__(self)
+        self.pspec = pspec
         self.pipe1 = LogicalStages(pspec)
         self._eqs = self.connect([self.pipe1])
 
diff --git a/src/soc/fu/mul/pipeline.py b/src/soc/fu/mul/pipeline.py
index 25745171..e726d170 100644
--- a/src/soc/fu/mul/pipeline.py
+++ b/src/soc/fu/mul/pipeline.py
@@ -20,6 +20,7 @@ class MulStages2(PipeModBaseChain):
 class ShiftRotBasePipe(ControlBase):
     def __init__(self, pspec):
         ControlBase.__init__(self)
+        self.pspec = pspec
         self.pipe1 = MulStages1(pspec)
         self.pipe2 = MulStages2(pspec)
         self._eqs = self.connect([self.pipe1, self.pipe2])
diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index 7023a781..5c34a692 100644
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -1,4 +1,4 @@
-from nmigen import Signal, Const
+from nmigen import Signal, Const, Cat
 from nmutil.dynamicpipe import SimpleHandshakeRedir
 from soc.fu.shift_rot.sr_input_record import CompSROpSubset
 from ieee754.fpcommon.getop import FPPipeContext
@@ -36,3 +36,8 @@ class ShiftRotInputData(IntegerData):
 class ShiftRotPipeSpec(CommonPipeSpec):
     regspec = (ShiftRotInputData.regspec, LogicalOutputData.regspec)
     opsubsetkls = CompSROpSubset
+    def rdflags(self, e): # in order of regspec input
+        reg1_ok = e.read_reg1.ok # RA
+        reg2_ok = e.read_reg2.ok # RB
+        reg3_ok = e.read_reg3.ok # RS
+        return Cat(reg1_ok, reg2_ok, reg3_ok, 1) # RA RB RC CA
diff --git a/src/soc/fu/shift_rot/pipeline.py b/src/soc/fu/shift_rot/pipeline.py
index 0449d37d..5121cb1e 100644
--- a/src/soc/fu/shift_rot/pipeline.py
+++ b/src/soc/fu/shift_rot/pipeline.py
@@ -15,6 +15,7 @@ class ShiftRotStages(PipeModBaseChain):
 class ShiftRotBasePipe(ControlBase):
     def __init__(self, pspec):
         ControlBase.__init__(self)
+        self.pspec = pspec
         self.pipe1 = ShiftRotStages(pspec)
         self._eqs = self.connect([self.pipe1])