From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 17 Jun 2020 14:55:04 +0000 (+0100)
Subject: get fu compunit test to use ISACaller instruction-memory
X-Git-Tag: div_pipeline~339
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=9453f40b89aa4cdcc7a2ba841ac83a4a6dd9fcda;hp=d97838711d21c329daf15c310de06ba5cb9f42ed

get fu compunit test to use ISACaller instruction-memory
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 51ae83c1..c62a32c3 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -226,6 +226,8 @@ class ISACaller:
             initial_insns = {}
             assert self.respect_pc == False, "instructions required to honor pc"
 
+        print ("ISACaller insns", respect_pc, initial_insns, disassembly)
+
         # "fake program counter" mode (for unit testing)
         if not respect_pc:
             if isinstance(initial_mem, tuple):
@@ -399,23 +401,24 @@ class ISACaller:
             pc = self.pc.CIA.value
         else:
             pc = self.fake_pc
-        ins = yield self.imem.ld(pc, 4, False)
-        yield self.pdecode2.dec.raw_opcode_in.eq(ins)
-        yield self.pdecode2.dec.bigendian.eq(0)  # little / big?
-        self._pc
+        self._pc = pc
+        ins = self.imem.ld(pc, 4, False)
+        print("setup: 0x{:X} 0x{:X}".format(pc, ins & 0xffffffff))
+
+        yield self.dec2.dec.raw_opcode_in.eq(ins)
+        yield self.dec2.dec.bigendian.eq(0)  # little / big?
 
     def execute_one(self):
         """execute one instruction
         """
         # get the disassembly code for this instruction
         code = self.disassembly[self._pc]
+        print("sim-execute", hex(self._pc), code)
         opname = code.split(' ')[0]
-        yield from call(opname)
+        yield from self.call(opname)
 
         if not self.respect_pc:
             self.fake_pc += 4
-        #else:
-            #self.pc.CIA.value = self.pc.NIA.value
 
     def call(self, name):
         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 5b03e2da..e1c7a8ca 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -182,11 +182,13 @@ class TestRunner(FHDLTestCase):
                 program = test.program
                 self.subTest(test.name)
                 print ("test", test.name, test.mem)
-                gen = program.generate_instructions()
+                gen = list(program.generate_instructions())
                 insncode = program.assembly.splitlines()
                 instructions = list(zip(gen, insncode))
                 sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
-                          test.msr)
+                          test.msr,
+                          initial_insns=gen, respect_pc=False,
+                          disassembly=insncode)
 
                 # initialise memory
                 if self.funit == Function.LDST:
@@ -195,9 +197,7 @@ class TestRunner(FHDLTestCase):
                 index = sim.pc.CIA.value//4
                 while index < len(instructions):
                     ins, code = instructions[index]
-                    yield simdec2.dec.raw_opcode_in.eq(ins)
-
-                    print("0x{:X} 0x{:X}".format(index*4, ins & 0xffffffff))
+                    yield from sim.setup_one()
                     print(code)
 
                     # ask the decoder to decode this binary data (endian'd)
@@ -244,8 +244,7 @@ class TestRunner(FHDLTestCase):
                             bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
 
                     # call simulated operation
-                    opname = code.split(' ')[0]
-                    yield from sim.call(opname)
+                    yield from sim.execute_one()
                     index = sim.pc.CIA.value//4
 
                     yield Settle()