From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 4 Aug 2020 15:42:54 +0000 (+0100)
Subject: msr and pc moved to "state" in PowerDecode2
X-Git-Tag: semi_working_ecp5~449
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=974e19953fac2ddc4cccabeab2797c7068da58a6

msr and pc moved to "state" in PowerDecode2
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 7a25bf0b..66e8ee49 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -513,8 +513,8 @@ class ISACaller:
 
         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
         yield self.dec2.dec.bigendian.eq(self.bigendian)
-        yield self.dec2.msr.eq(self.msr.value)
-        yield self.dec2.cia.eq(pc)
+        yield self.dec2.state.msr.eq(self.msr.value)
+        yield self.dec2.state.pc.eq(pc)
 
     def execute_one(self):
         """execute one instruction
diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 393e445b..3af4bb50 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -209,8 +209,8 @@ class TestRunner(FHDLTestCase):
 
             # ask the decoder to decode this binary data (endian'd)
             yield pdecode2.dec.bigendian.eq(self.bigendian)  # le / be?
-            yield pdecode2.msr.eq(msr)  # set MSR "state"
-            yield pdecode2.cia.eq(pc)  # set PC "state"
+            yield pdecode2.state.msr.eq(msr)  # set MSR "state"
+            yield pdecode2.state.pc.eq(pc)  # set PC "state"
             yield instruction.eq(ins)          # raw binary instr.
             yield Settle()
             # debugging issue with branch