From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 22 Aug 2020 14:39:29 +0000 (+0100)
Subject: bug in andc and orc, complement was taking place on RA not RB
X-Git-Tag: semi_working_ecp5~272^2~26
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=c5a69c8b06df9ab639435dcb2386122dbd6c67f0

bug in andc and orc, complement was taking place on RA not RB
---

diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py
index 745be772..1b64e5ce 100644
--- a/src/soc/fu/common_input_stage.py
+++ b/src/soc/fu/common_input_stage.py
@@ -19,7 +19,11 @@ class CommonInputStage(PipeModBase):
         # operand a to be as-is or inverted
         a = Signal.like(self.i.a)
 
-        if hasattr(op, "invert_a"):
+        op_to_invert = 'ra'
+        if hasattr(self, "invert_op"):
+            op_to_invert = self.invert_op
+
+        if hasattr(op, "invert_a") and op_to_invert == 'ra':
             with m.If(op.invert_a):
                 comb += a.eq(~self.i.a)
             with m.Else():
@@ -29,6 +33,21 @@ class CommonInputStage(PipeModBase):
 
         comb += self.o.a.eq(a)
 
+        ##### operand B #####
+
+        # operand b to be as-is or inverted
+        b = Signal.like(self.i.b)
+
+        if hasattr(op, "invert_a") and op_to_invert == 'rb':
+            with m.If(op.invert_a):
+                comb += b.eq(~self.i.b)
+            with m.Else():
+                comb += b.eq(self.i.b)
+        else:
+            comb += b.eq(self.i.b)
+
+        comb += self.o.b.eq(b)
+
         ##### carry-in #####
 
         # either copy incoming carry or set to 1/0 as defined by op
diff --git a/src/soc/fu/logical/input_stage.py b/src/soc/fu/logical/input_stage.py
index df281877..43f20c6e 100644
--- a/src/soc/fu/logical/input_stage.py
+++ b/src/soc/fu/logical/input_stage.py
@@ -9,6 +9,7 @@ from soc.fu.logical.pipe_data import LogicalInputData
 class LogicalInputStage(CommonInputStage):
     def __init__(self, pspec):
         super().__init__(pspec, "input")
+        self.invert_op = "rb" # inversion is on register b
 
     def ispec(self):
         return LogicalInputData(self.pspec)
@@ -17,11 +18,8 @@ class LogicalInputStage(CommonInputStage):
         return LogicalInputData(self.pspec)
 
     def elaborate(self, platform):
-        m = super().elaborate(platform) # covers A-invert, carry, excludes SO
+        m = super().elaborate(platform) # covers B-invert, carry, excludes SO
         comb = m.d.comb
         ctx = self.i.ctx
 
-        # operand b
-        comb += self.o.b.eq(self.i.b)
-
         return m
diff --git a/src/soc/fu/shift_rot/input_stage.py b/src/soc/fu/shift_rot/input_stage.py
index f195b40e..06055540 100644
--- a/src/soc/fu/shift_rot/input_stage.py
+++ b/src/soc/fu/shift_rot/input_stage.py
@@ -20,8 +20,7 @@ class ShiftRotInputStage(CommonInputStage):
         m = super().elaborate(platform) # handles A, carry and sticky overflow
         comb = m.d.comb
 
-        # operands ra and rb
-        comb += self.o.rb.eq(self.i.rb)
+        # operand rs
         comb += self.o.rs.eq(self.i.rs)
 
         return m
diff --git a/src/soc/fu/shift_rot/pipe_data.py b/src/soc/fu/shift_rot/pipe_data.py
index 280a7575..04776296 100644
--- a/src/soc/fu/shift_rot/pipe_data.py
+++ b/src/soc/fu/shift_rot/pipe_data.py
@@ -11,7 +11,8 @@ class ShiftRotInputData(IntegerData):
     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience
-        self.a, self.rs = self.ra, self.rc
+        self.a, self.b, self.rs = self.ra, self.rb, self.rc
+
 
 
 class ShiftRotPipeSpec(CommonPipeSpec):