From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 17 Jun 2020 14:40:46 +0000 (+0100)
Subject: split execute and setup of ISACaller instruction execution
X-Git-Tag: div_pipeline~341
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=d437d98d02ef2d7ac143f74a8c759cc35e0cfbed

split execute and setup of ISACaller instruction execution
into two phases
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index ec6af39c..51ae83c1 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -226,7 +226,6 @@ class ISACaller:
             initial_insns = {}
             assert self.respect_pc == False, "instructions required to honor pc"
 
-
         # "fake program counter" mode (for unit testing)
         if not respect_pc:
             if isinstance(initial_mem, tuple):
@@ -393,18 +392,31 @@ class ISACaller:
         self.namespace['NIA'] = SelectableInt(pc_val, 64)
         self.pc.update(self.namespace)
 
-    def execute_one(self):
+    def setup_one(self):
+        """set up one instruction
+        """
         if self.respect_pc:
             pc = self.pc.CIA.value
         else:
             pc = self.fake_pc
-            self.fake_pc += 4
         ins = yield self.imem.ld(pc, 4, False)
         yield self.pdecode2.dec.raw_opcode_in.eq(ins)
         yield self.pdecode2.dec.bigendian.eq(0)  # little / big?
+        self._pc
+
+    def execute_one(self):
+        """execute one instruction
+        """
+        # get the disassembly code for this instruction
+        code = self.disassembly[self._pc]
         opname = code.split(' ')[0]
         yield from call(opname)
 
+        if not self.respect_pc:
+            self.fake_pc += 4
+        #else:
+            #self.pc.CIA.value = self.pc.NIA.value
+
     def call(self, name):
         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282