From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 23 Jan 2021 21:30:30 +0000 (+0000)
Subject: check src/dest mask exist if zeroing, svp64
X-Git-Tag: 24jan2021_ls180~3
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=d76850eb53a56a7d6f27b7fde08fb9f05e3ece0e

check src/dest mask exist if zeroing, svp64
---

diff --git a/src/soc/sv/trans/svp64.py b/src/soc/sv/trans/svp64.py
index e2e1870b..e598c9bb 100644
--- a/src/soc/sv/trans/svp64.py
+++ b/src/soc/sv/trans/svp64.py
@@ -477,6 +477,11 @@ class SVP64:
                 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
                 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
 
+            if src_zero:
+                assert has_smask, "src zeroing requires a source predicate"
+            if dst_zero:
+                assert has_pmask, "dest zeroing requires a dest predicate"
+
             # "normal" mode
             if sv_mode is None:
                 mode |= (src_zero << 3) | (dst_zero << 4) # predicate zeroing
@@ -596,7 +601,7 @@ if __name__ == '__main__':
                  'sv.setb/vec2 5, 31',
                  'sv.setb/sw=8.ew=16 5, 31',
                  'sv.extsw./ff=eq 5, 31',
-                 'sv.extsw./satu.sz.dz 5, 31',
+                 'sv.extsw./satu.sz.dz.sm=r3.m=r3 5, 31',
                  'sv.extsw./pr=eq 5.v, 31',
                 ])
     csvs = SVP64RM()