From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 5 Mar 2021 21:08:28 +0000 (+0000)
Subject: litex expects wishbone "err" signals even if not used
X-Git-Tag: convert-csv-opcode-to-binary~107
X-Git-Url: https://git.libre-soc.org/?p=soc.git;a=commitdiff_plain;h=ff07bed9aa31ac012f25bda6a3b6f62396702cd1

litex expects wishbone "err" signals even if not used
---

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 07a460e3..72b432da 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -85,7 +85,8 @@ class TestIssuerInternal(Elaboratable):
         if self.sram4x4k:
             self.sram4k = []
             for i in range(4):
-                self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i))
+                self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
+                                                    features={'err'}))
 
         # add interrupt controller?
         self.xics = hasattr(pspec, "xics") and pspec.xics == True