Add ability to specify initial state for SPRs
[soc.git] / src / soc / alu / test / test_pipe_caller.py
2020-05-11 Michael NolanAdd ability to specify initial state for SPRs
2020-05-11 Michael NolanFix rlwimi by reordering the inputs *again*
2020-05-11 Michael NolanRe-enable rlwinm test
2020-05-11 Michael NolanCheck write register number too
2020-05-11 Michael NolanReorder the register reads so the field in read_reg2...
2020-05-11 Michael NolanHave test_pipe_caller actually read from the registers...
2020-05-10 Michael NolanAdd test for rlwnm
2020-05-10 Michael NolanImplement rlwimi as well
2020-05-10 Michael NolanImplement rlwinm in alu
2020-05-09 Michael NolanAdd shift left and shift right to main stage proof
2020-05-09 Michael NolanHandle algebraic shifts too
2020-05-09 Michael NolanImplement logical shift right
2020-05-09 Michael NolanAdd support for sld
2020-05-09 Michael NolanChange shift left to be implemented with rotate and...
2020-05-09 Michael NolanAdd mask generator for shift class instructions
2020-05-09 Michael NolanAdd shift left opcode to main_stage
2020-05-09 Michael NolanMinor cleanup
2020-05-08 Michael NolanAdd tests for immediates, add subf to tests
2020-05-08 Michael NolanAdd test for alu against simulator