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Add ability to specify initial state for SPRs
[soc.git]
/
src
/
soc
/
alu
/
test
/
test_pipe_caller.py
2020-05-11
Michael Nolan
Add ability to specify initial state for SPRs
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2020-05-11
Michael Nolan
Fix rlwimi by reordering the inputs *again*
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2020-05-11
Michael Nolan
Re-enable rlwinm test
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2020-05-11
Michael Nolan
Check write register number too
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2020-05-11
Michael Nolan
Reorder the register reads so the field in read_reg2...
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2020-05-11
Michael Nolan
Have test_pipe_caller actually read from the registers...
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2020-05-10
Michael Nolan
Add test for rlwnm
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2020-05-10
Michael Nolan
Implement rlwimi as well
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2020-05-10
Michael Nolan
Implement rlwinm in alu
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2020-05-09
Michael Nolan
Add shift left and shift right to main stage proof
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2020-05-09
Michael Nolan
Handle algebraic shifts too
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2020-05-09
Michael Nolan
Implement logical shift right
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2020-05-09
Michael Nolan
Add support for sld
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2020-05-09
Michael Nolan
Change shift left to be implemented with rotate and...
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2020-05-09
Michael Nolan
Add mask generator for shift class instructions
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2020-05-09
Michael Nolan
Add shift left opcode to main_stage
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2020-05-09
Michael Nolan
Minor cleanup
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2020-05-08
Michael Nolan
Add tests for immediates, add subf to tests
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2020-05-08
Michael Nolan
Add test for alu against simulator
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