projects
/
soc.git
/ history
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
first ⋅ prev ⋅ next
fetch instructions from bare wishbone fetch unit
[soc.git]
/
src
/
soc
/
bus
/
test
/
test_minerva.py
2020-06-29
Luke Kenneth Casso...
fetch instructions from bare wishbone fetch unit
blob
|
commitdiff
|
raw
2020-06-28
Luke Kenneth Casso...
sram address do not cut by LSBs
blob
|
commitdiff
|
raw
|
diff to current
2020-06-27
Luke Kenneth Casso...
make Memory accessible via TestSRAMBareLoadStoreUnit
blob
|
commitdiff
|
raw
|
diff to current
2020-06-26
Luke Kenneth Casso...
investigating why write-enable not getting passed through
blob
|
commitdiff
|
raw
|
diff to current
2020-06-26
Luke Kenneth Casso...
whoops forgot to call parent elaborate
blob
|
commitdiff
|
raw
|
diff to current
2020-06-26
Luke Kenneth Casso...
add test of SRAM through wishbone bus
blob
|
commitdiff
|
raw
|
diff to current
2020-06-26
Luke Kenneth Casso...
code-morph which redirects lsmem unit test through...
blob
|
commitdiff
|
raw
|
diff to current
2020-06-26
Luke Kenneth Casso...
add a test SRAM that lives behind a minerva LoadStoreUn...
blob
|
commitdiff
|
raw
|
diff to current