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attempting to add SPRs to rfid test
[soc.git] / src / soc / bus /
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit tree | commitdiff
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface tree | commitdiff
2020-06-28 Luke Kenneth Casso... sram address do not cut by LSBs tree | commitdiff
2020-06-27 Luke Kenneth Casso... make Memory accessible via TestSRAMBareLoadStoreUnit tree | commitdiff
2020-06-26 Luke Kenneth Casso... investigating why write-enable not getting passed through tree | commitdiff
2020-06-26 Luke Kenneth Casso... whoops forgot to call parent elaborate tree | commitdiff
2020-06-26 Luke Kenneth Casso... add test of SRAM through wishbone bus tree | commitdiff
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through... tree | commitdiff
2020-06-26 Luke Kenneth Casso... add a test SRAM that lives behind a minerva LoadStoreUn... tree | commitdiff
2020-06-20 Luke Kenneth Casso... expand Memory width to 64 and granularity to 16 in... tree | commitdiff
2020-06-20 Luke Kenneth Casso... add asserts to check data output is correct tree | commitdiff
2020-06-20 Luke Kenneth Casso... add test_sram_wishbone.py tree | commitdiff