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[soc.git] / src / soc / bus /
2020-12-20 Cesar StraussAdd support for CXXSim simulation tree | commitdiff
2020-09-05 Luke Kenneth Casso... add simple GPIO wishbone bus to litex sim.py tree | commitdiff
2020-09-05 Luke Kenneth Casso... move wb read/write to separate util test library and... tree | commitdiff
2020-09-05 Luke Kenneth Casso... add simple wishbone GPIO peripheral tree | commitdiff
2020-08-21 Luke Kenneth Casso... ld/st bus reduction test operational tree | commitdiff
2020-08-21 Luke Kenneth Casso... first test of down-converted load/store from 64 to... tree | commitdiff
2020-08-21 Luke Kenneth Casso... first test of down-converted load/store from 64 to... tree | commitdiff
2020-08-21 Luke Kenneth Casso... add in WishboneDownConvert into LoadStoreUnitInterface tree | commitdiff
2020-08-21 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2020-08-20 Luke Kenneth Casso... bugfix wishbone downconvert using wb sram 64-to-32... tree | commitdiff
2020-08-20 Luke Kenneth Casso... add a wishbone upconverter tree | commitdiff
2020-07-29 Jacob Lifshayadd __init__.py to all source directories tree | commitdiff
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master' tree | commitdiff
2020-07-22 Jacob Lifshayformat code tree | commitdiff
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2020-07-07 Luke Kenneth Casso... whoops error in test of dynamic parameter tree | commitdiff
2020-07-07 Luke Kenneth Casso... sort-of got binary execution test working tree | commitdiff
2020-07-07 Luke Kenneth Casso... code-shuffle on testing to prepare loading large files... tree | commitdiff
2020-07-01 Luke Kenneth Casso... minor reorg on how Bus and Config classes are set up tree | commitdiff
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit tree | commitdiff
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface tree | commitdiff
2020-06-28 Luke Kenneth Casso... sram address do not cut by LSBs tree | commitdiff
2020-06-27 Luke Kenneth Casso... make Memory accessible via TestSRAMBareLoadStoreUnit tree | commitdiff
2020-06-26 Luke Kenneth Casso... investigating why write-enable not getting passed through tree | commitdiff
2020-06-26 Luke Kenneth Casso... whoops forgot to call parent elaborate tree | commitdiff
2020-06-26 Luke Kenneth Casso... add test of SRAM through wishbone bus tree | commitdiff
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through... tree | commitdiff
2020-06-26 Luke Kenneth Casso... add a test SRAM that lives behind a minerva LoadStoreUn... tree | commitdiff
2020-06-20 Luke Kenneth Casso... expand Memory width to 64 and granularity to 16 in... tree | commitdiff
2020-06-20 Luke Kenneth Casso... add asserts to check data output is correct tree | commitdiff
2020-06-20 Luke Kenneth Casso... add test_sram_wishbone.py tree | commitdiff