replace PartitionedSignal with SimdSignal
[soc.git] / src / soc / bus /
2021-05-27 Luke Kenneth Casso... corrections on spblock ack
2021-05-27 Luke Kenneth Casso... classic wishbone mode: must not do ack if already acked
2021-05-24 Luke Kenneth Casso... whoops sort out name of SPBlock RAM
2021-05-02 Luke Kenneth Casso... quick hack to SRAM test and to dcache to enable classic...
2021-04-30 Luke Kenneth Casso... sort out spblock 4k sram cell instance name to match...
2021-04-26 Luke Kenneth Casso... comment read ack in sram
2021-04-20 Luke Kenneth Casso... use soc.bus.sram instead of nmigen_soc.wishbone.sram
2021-04-20 Luke Kenneth Casso... add wishbone sram.py (move from nmigen-soc)
2021-04-19 Luke Kenneth Casso... give independent names to spblock512w64b8ws
2021-04-18 Luke Kenneth Casso... give spblock512 a name as a submodule
2021-04-18 Luke Kenneth Casso... rename SPBlock_512W64B8W to lowercase
2021-04-06 Luke Kenneth Casso... 4k SRAM Instance needs write-enable @ 8-bit width
2021-03-06 Luke Kenneth Casso... remove blackbox attribute on SPBlock_512W64B8W
2021-03-05 Luke Kenneth Casso... extend name of sram4k block with _wb suffix
2021-02-21 Luke Kenneth Casso... add JTAG enable/disable of 4k SRAMs
2021-02-20 Luke Kenneth Casso... add black-box attribute to 4k SRAM cell
2021-02-20 Luke Kenneth Casso... add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer...
2021-02-20 Luke Kenneth Casso... add Wishbone-wrapped SPBlock_512W64B8W
2020-12-20 Cesar StraussAdd support for CXXSim simulation
2020-09-05 Luke Kenneth Casso... add simple GPIO wishbone bus to litex sim.py
2020-09-05 Luke Kenneth Casso... move wb read/write to separate util test library and...
2020-09-05 Luke Kenneth Casso... add simple wishbone GPIO peripheral
2020-08-21 Luke Kenneth Casso... ld/st bus reduction test operational
2020-08-21 Luke Kenneth Casso... first test of down-converted load/store from 64 to...
2020-08-21 Luke Kenneth Casso... first test of down-converted load/store from 64 to...
2020-08-21 Luke Kenneth Casso... add in WishboneDownConvert into LoadStoreUnitInterface
2020-08-21 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-20 Luke Kenneth Casso... bugfix wishbone downconvert using wb sram 64-to-32...
2020-08-20 Luke Kenneth Casso... add a wishbone upconverter
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... whoops error in test of dynamic parameter
2020-07-07 Luke Kenneth Casso... sort-of got binary execution test working
2020-07-07 Luke Kenneth Casso... code-shuffle on testing to prepare loading large files...
2020-07-01 Luke Kenneth Casso... minor reorg on how Bus and Config classes are set up
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit
2020-06-28 Luke Kenneth Casso... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth Casso... sram address do not cut by LSBs
2020-06-27 Luke Kenneth Casso... make Memory accessible via TestSRAMBareLoadStoreUnit
2020-06-26 Luke Kenneth Casso... investigating why write-enable not getting passed through
2020-06-26 Luke Kenneth Casso... whoops forgot to call parent elaborate
2020-06-26 Luke Kenneth Casso... add test of SRAM through wishbone bus
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through...
2020-06-26 Luke Kenneth Casso... add a test SRAM that lives behind a minerva LoadStoreUn...
2020-06-20 Luke Kenneth Casso... expand Memory width to 64 and granularity to 16 in...
2020-06-20 Luke Kenneth Casso... add asserts to check data output is correct
2020-06-20 Luke Kenneth Casso... add test_sram_wishbone.py