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add separate DummyPLL module, according to API discussed at
[soc.git] / src / soc / clock / select.py
2020-11-10 Luke Kenneth Casso... add separate DummyPLL module, according to API discussed at blob | commitdiff | raw
2020-10-07 Luke Kenneth Casso... reorder / reorganise reset signals slightly blob | commitdiff | raw | diff to current
2020-10-06 Luke Kenneth Casso... add ports function to DummyPLL blob | commitdiff | raw | diff to current
2020-10-01 Luke Kenneth Casso... create dummy PLL block, connect up to core and clock... blob | commitdiff | raw | diff to current
2020-09-27 Luke Kenneth Casso... rename sys_clk_i to clk_24_i blob | commitdiff | raw | diff to current
2020-09-27 Luke Kenneth Casso... add clock selection mechanism blob | commitdiff | raw | diff to current