radix: reading first page table entry
[soc.git] / src / soc / clock /
2020-11-13 Luke Kenneth Casso... reduce clkcsel ls180 width (2 pins), rename pll_18...
2020-11-13 Luke Kenneth Casso... rename and add pll lock signal to ls180
2020-11-10 Luke Kenneth Casso... remove ClockSelect module, use DummyPLL
2020-11-10 Luke Kenneth Casso... add separate DummyPLL module, according to API discussed at
2020-10-07 Luke Kenneth Casso... reorder / reorganise reset signals slightly
2020-10-06 Luke Kenneth Casso... add ports function to DummyPLL
2020-10-01 Luke Kenneth Casso... create dummy PLL block, connect up to core and clock...
2020-09-27 Luke Kenneth Casso... rename sys_clk_i to clk_24_i
2020-09-27 Luke Kenneth Casso... add clock selection mechanism