radix: reading first page table entry
[soc.git] / src / soc / config /
2021-02-26 Luke Kenneth Casso... comment on CoreState
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-14 Luke Kenneth Casso... add SVSTATE to CoreState
2020-10-04 Luke Kenneth Casso... significant reorg of the litex pinspecs to use pinmux...
2020-10-04 Luke Kenneth Casso... submodule update
2020-09-06 Luke Kenneth Casso... add DEC SPR to CoreState and PowerDecoder, activate...
2020-09-04 Luke Kenneth Casso... adding option to include XICS external interrupts.
2020-08-21 Luke Kenneth Casso... ld/st bus reduction test operational
2020-08-21 Luke Kenneth Casso... first test of down-converted load/store from 64 to...
2020-08-03 Luke Kenneth Casso... use new soc.config.state CoreState class in DMI and...
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-29 Jacob Lifshayclean up some tests
2020-07-29 Jacob Lifshayformat some tests
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-15 Luke Kenneth Casso... add better comments on mul overflow
2020-07-15 Luke Kenneth Casso... test privileged rfid call
2020-07-11 Luke Kenneth Casso... add bigendian mode to helloworld test
2020-07-11 Luke Kenneth Casso... sort out big/little endian startup on qemu
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... code-shuffle on testing to prepare loading large files...
2020-07-02 Luke Kenneth Casso... use Mock class (more convenient)
2020-07-02 Luke Kenneth Casso... add bare wishbone option to TestIssuer, sort out ports
2020-07-01 Luke Kenneth Casso... minor reorg on how Bus and Config classes are set up
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit
2020-06-28 Luke Kenneth Casso... add Config Fetch interface and quick unit test
2020-06-27 Luke Kenneth Casso... unit test in l0_cache to connect to testpi and test_bare_wb
2020-06-27 Luke Kenneth Casso... fix TestMemLoadStoreUnit, it required a FSM to monitor...
2020-06-27 Luke Kenneth Casso... add wishbone Pi2LSUI test
2020-06-27 Luke Kenneth Casso... reconfigureable PortInterface testing now possible
2020-06-26 Luke Kenneth Casso... load/store unit test needed to wait for busy_o
2020-06-26 Luke Kenneth Casso... investigating why write-enable not getting passed through
2020-06-26 Luke Kenneth Casso... whoops forgot to call parent elaborate
2020-06-26 Luke Kenneth Casso... add test of SRAM through wishbone bus
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through...
2020-06-26 Luke Kenneth Casso... add a test SRAM that lives behind a minerva LoadStoreUn...
2020-06-26 Luke Kenneth Casso... add reconfigureable Load/Store class