also read LDST RM files
[soc.git] / src / soc / consts.py
2020-10-06 Luke Kenneth Casso... add SRR1 setting for LDST memory exception trap
2020-10-06 Luke Kenneth Casso... add LDSTException decode/handling in PowerDecoder2
2020-09-06 Luke Kenneth Casso... add DEC SPR to CoreState and PowerDecoder, activate...
2020-09-04 Luke Kenneth Casso... adding option to include XICS external interrupts.
2020-07-24 Samuel A. Falvo IIWIP: addressing code review, restoring proofs, etc.
2020-07-24 Luke Kenneth Casso... add better comments on field_slice
2020-07-24 Luke Kenneth Casso... returned field_slice to original, and added comments
2020-07-24 Luke Kenneth Casso... made it clear what is meant by the slice numbering...
2020-07-24 Samuel A. Falvo IIRefactorin of common code
2020-07-22 Luke Kenneth Casso... sigh, auto-create some little/big-endian classes for...
2020-07-22 Luke Kenneth Casso... add TT.size and use it in PowerDecoder and trap input...
2020-07-22 Luke Kenneth Casso... note that traptype MUST increase in bitwidth correspond...
2020-07-22 Samuel A. Falvo IIComplete FV properties for OP_TRAP instructions.
2020-07-21 Samuel A. Falvo IIRefine properties to comply with spec
2020-07-21 Samuel A. Falvo IIMerge in recent updates to TRAP FV properties.
2020-07-15 Luke Kenneth Casso... move traptype to soc.consts
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-04 Luke Kenneth Casso... cater for illegal instruction (generates a trap)
2020-07-04 Luke Kenneth Casso... use new consts module