add SVSTATE read to DMI interface
[soc.git] / src / soc / debug / dmi.py
2021-03-07 Luke Kenneth Casso... add SVSTATE read to DMI interface
2020-09-22 Luke Kenneth Casso... add jtag interface to issuer_verilog
2020-09-21 Luke Kenneth Casso... arg complete rewrite of JTAG2DMI, based it on staf...
2020-08-29 Luke Kenneth Casso... add hack to get at XER through DMI interface
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-25 Luke Kenneth Casso... add CR read to DMI interface
2020-08-25 Luke Kenneth Casso... shorten using temp vars
2020-08-25 Luke Kenneth Casso... add CR DMI interface
2020-08-03 Luke Kenneth Casso... add quick demo/test of reading DMI reg 9
2020-08-03 Luke Kenneth Casso... use new soc.config.state CoreState class in DMI and...
2020-08-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-08-03 Luke Kenneth Casso... move debug to record
2020-08-02 Luke Kenneth Casso... convert microwatt core_debug.vhdl to nmigen